cf_fft_2048_18.map.qmsg

2048点的fft的算法源程序

{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9445) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9445): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9445 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9510) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9510): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9510 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9535) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9535): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9535 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9542) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9542): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9542 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9567) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9567): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9567 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9592) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9592): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9592 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9599) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9599): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9599 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9608) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9608): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9608 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9617) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9617): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9617 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_35 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26 " "Info: Elaborating entity \"cf_fft_2048_18_35\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\"" {  } { { "cf_fft_2048_18.v" "s26" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 8723 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9132) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9132): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9132 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_39 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_39:s6 " "Info: Elaborating entity \"cf_fft_2048_18_39\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_39:s6\"" {  } { { "cf_fft_2048_18.v" "s6" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9138 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_40 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_39:s6\|cf_fft_2048_18_40:s10 " "Info: Elaborating entity \"cf_fft_2048_18_40\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_39:s6\|cf_fft_2048_18_40:s10\"" {  } { { "cf_fft_2048_18.v" "s10" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9259 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_38 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_38:s7 " "Info: Elaborating entity \"cf_fft_2048_18_38\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_38:s7\"" {  } { { "cf_fft_2048_18.v" "s7" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9139 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_36 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_36:s8 " "Info: Elaborating entity \"cf_fft_2048_18_36\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_36:s8\"" {  } { { "cf_fft_2048_18.v" "s8" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9140 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_37 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_36:s8\|cf_fft_2048_18_37:s8 " "Info: Elaborating entity \"cf_fft_2048_18_37\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_35:s26\|cf_fft_2048_18_36:s8\|cf_fft_2048_18_37:s8\"" {  } { { "cf_fft_2048_18.v" "s8" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9162 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_31 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27 " "Info: Elaborating entity \"cf_fft_2048_18_31\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\"" {  } { { "cf_fft_2048_18.v" "s27" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 8724 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(8988) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(8988): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 8988 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(8996) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(8996): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 8996 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9005) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9005): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9005 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9013) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9013): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9013 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_32 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12 " "Info: Elaborating entity \"cf_fft_2048_18_32\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12\"" {  } { { "cf_fft_2048_18.v" "s12" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9021 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "cf_fft_2048_18.v(9044) " "Warning (10101): Verilog HDL unsupported feature warning at cf_fft_2048_18.v(9044): Initial Construct is not supported and will be ignored" {  } { { "cf_fft_2048_18.v" "" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9044 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_34 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12\|cf_fft_2048_18_34:s7 " "Info: Elaborating entity \"cf_fft_2048_18_34\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12\|cf_fft_2048_18_34:s7\"" {  } { { "cf_fft_2048_18.v" "s7" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9050 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_33 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12\|cf_fft_2048_18_33:s8 " "Info: Elaborating entity \"cf_fft_2048_18_33\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_31:s27\|cf_fft_2048_18_32:s12\|cf_fft_2048_18_33:s8\"" {  } { { "cf_fft_2048_18.v" "s8" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 9051 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cf_fft_2048_18_30 cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_30:s28 " "Info: Elaborating entity \"cf_fft_2048_18_30\" for hierarchy \"cf_fft_2048_18_1:s1\|cf_fft_2048_18_25:s1\|cf_fft_2048_18_30:s28\"" {  } { { "cf_fft_2048_18.v" "s28" { Text "E:/图像处理资料/cf_fft_2048_18/cf_fft_2048_18.v" 8725 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}