cf_fft_2048_18.v

2048点的fft的算法源程序

  s27_1[53],
  s27_1[52],
  s27_1[51],
  s27_1[50],
  s27_1[49],
  s27_1[48],
  s27_1[47],
  s27_1[46],
  s27_1[45],
  s27_1[44],
  s27_1[43],
  s27_1[42],
  s27_1[41],
  s27_1[40],
  s27_1[39],
  s27_1[38],
  s27_1[37],
  s27_1[36]};
assign n22 = {s27_1[35],
  s27_1[34],
  s27_1[33],
  s27_1[32],
  s27_1[31],
  s27_1[30],
  s27_1[29],
  s27_1[28],
  s27_1[27],
  s27_1[26],
  s27_1[25],
  s27_1[24],
  s27_1[23],
  s27_1[22],
  s27_1[21],
  s27_1[20],
  s27_1[19],
  s27_1[18],
  s27_1[17],
  s27_1[16],
  s27_1[15],
  s27_1[14],
  s27_1[13],
  s27_1[12],
  s27_1[11],
  s27_1[10],
  s27_1[9],
  s27_1[8],
  s27_1[7],
  s27_1[6],
  s27_1[5],
  s27_1[4],
  s27_1[3],
  s27_1[2],
  s27_1[1],
  s27_1[0]};
assign n23 = s26_1 ? n20 : n19;
assign n24 = s26_1 ? n22 : n21;
cf_fft_2048_18_7 s25 (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);
cf_fft_2048_18_35 s26 (clock_c, n18, i4, i5, s26_1);
cf_fft_2048_18_31 s27 (clock_c, n2, n6, n11, n16, i4, i5, s27_1);
cf_fft_2048_18_30 s28 (clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3);
cf_fft_2048_18_26 s29 (clock_c, i1, i4, i5, s29_1, s29_2);
assign o3 = n24;
assign o2 = n23;
assign o1 = s28_1;
endmodule

module cf_fft_2048_18_6 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);
input  clock_c;
input  i1;
input  [35:0] i2;
input  [35:0] i3;
input  i4;
input  i5;
output o1;
output [35:0] o2;
output [35:0] o3;
wire   n1;
wire   [71:0] n2;
reg    n3;
reg    n4;
reg    n5;
reg    n6;
wire   [8:0] n7;
reg    [8:0] n8;
reg    [8:0] n9;
reg    [8:0] n10;
reg    [8:0] n11;
wire   n12;
reg    n13;
reg    n14;
reg    n15;
reg    n16;
wire   n17;
wire   [1:0] n18;
wire   [35:0] n19;
wire   [35:0] n20;
wire   [35:0] n21;
wire   [35:0] n22;
wire   [35:0] n23;
wire   [35:0] n24;
wire   [35:0] s25_1;
wire   [35:0] s25_2;
wire   s26_1;
wire   [71:0] s27_1;
wire   s28_1;
wire   s28_2;
wire   [71:0] s28_3;
wire   [9:0] s29_1;
wire   s29_2;
assign n1 = s29_1[9];
assign n2 = {s25_1, s25_2};
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n3 <= 1'b0;
  else if (i4 == 1'b1)
    n3 <= s29_2;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n4 <= 1'b0;
  else if (i4 == 1'b1)
    n4 <= n3;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n5 <= 1'b0;
  else if (i4 == 1'b1)
    n5 <= n4;
initial n6 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n6 <= 1'b0;
  else if (i4 == 1'b1)
    n6 <= n5;
assign n7 = {s29_1[9],
  s29_1[8],
  s29_1[7],
  s29_1[6],
  s29_1[5],
  s29_1[4],
  s29_1[3],
  s29_1[2],
  s29_1[1]};
initial n8 = 9'b000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n8 <= 9'b000000000;
  else if (i4 == 1'b1)
    n8 <= n7;
initial n9 = 9'b000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n9 <= 9'b000000000;
  else if (i4 == 1'b1)
    n9 <= n8;
initial n10 = 9'b000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n10 <= 9'b000000000;
  else if (i4 == 1'b1)
    n10 <= n9;
initial n11 = 9'b000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n11 <= 9'b000000000;
  else if (i4 == 1'b1)
    n11 <= n10;
assign n12 = s29_1[0];
initial n13 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n13 <= 1'b0;
  else if (i4 == 1'b1)
    n13 <= n12;
initial n14 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n14 <= 1'b0;
  else if (i4 == 1'b1)
    n14 <= n13;
initial n15 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n15 <= 1'b0;
  else if (i4 == 1'b1)
    n15 <= n14;
initial n16 = 1'b0;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n16 <= 1'b0;
  else if (i4 == 1'b1)
    n16 <= n15;
assign n17 = ~n16;
assign n18 = {s28_2, s28_1};
assign n19 = {s28_3[71],
  s28_3[70],
  s28_3[69],
  s28_3[68],
  s28_3[67],
  s28_3[66],
  s28_3[65],
  s28_3[64],
  s28_3[63],
  s28_3[62],
  s28_3[61],
  s28_3[60],
  s28_3[59],
  s28_3[58],
  s28_3[57],
  s28_3[56],
  s28_3[55],
  s28_3[54],
  s28_3[53],
  s28_3[52],
  s28_3[51],
  s28_3[50],
  s28_3[49],
  s28_3[48],
  s28_3[47],
  s28_3[46],
  s28_3[45],
  s28_3[44],
  s28_3[43],
  s28_3[42],
  s28_3[41],
  s28_3[40],
  s28_3[39],
  s28_3[38],
  s28_3[37],
  s28_3[36]};
assign n20 = {s28_3[35],
  s28_3[34],
  s28_3[33],
  s28_3[32],
  s28_3[31],
  s28_3[30],
  s28_3[29],
  s28_3[28],
  s28_3[27],
  s28_3[26],
  s28_3[25],
  s28_3[24],
  s28_3[23],
  s28_3[22],
  s28_3[21],
  s28_3[20],
  s28_3[19],
  s28_3[18],
  s28_3[17],
  s28_3[16],
  s28_3[15],
  s28_3[14],
  s28_3[13],
  s28_3[12],
  s28_3[11],
  s28_3[10],
  s28_3[9],
  s28_3[8],
  s28_3[7],
  s28_3[6],
  s28_3[5],
  s28_3[4],
  s28_3[3],
  s28_3[2],
  s28_3[1],
  s28_3[0]};
assign n21 = {s27_1[71],
  s27_1[70],
  s27_1[69],
  s27_1[68],
  s27_1[67],
  s27_1[66],
  s27_1[65],
  s27_1[64],
  s27_1[63],
  s27_1[62],
  s27_1[61],
  s27_1[60],
  s27_1[59],
  s27_1[58],
  s27_1[57],
  s27_1[56],
  s27_1[55],
  s27_1[54],
  s27_1[53],
  s27_1[52],
  s27_1[51],
  s27_1[50],
  s27_1[49],
  s27_1[48],
  s27_1[47],
  s27_1[46],
  s27_1[45],
  s27_1[44],
  s27_1[43],
  s27_1[42],
  s27_1[41],
  s27_1[40],
  s27_1[39],
  s27_1[38],
  s27_1[37],
  s27_1[36]};
assign n22 = {s27_1[35],
  s27_1[34],
  s27_1[33],
  s27_1[32],
  s27_1[31],
  s27_1[30],
  s27_1[29],
  s27_1[28],
  s27_1[27],
  s27_1[26],
  s27_1[25],
  s27_1[24],
  s27_1[23],
  s27_1[22],
  s27_1[21],
  s27_1[20],
  s27_1[19],
  s27_1[18],
  s27_1[17],
  s27_1[16],
  s27_1[15],
  s27_1[14],
  s27_1[13],
  s27_1[12],
  s27_1[11],
  s27_1[10],
  s27_1[9],
  s27_1[8],
  s27_1[7],
  s27_1[6],
  s27_1[5],
  s27_1[4],
  s27_1[3],
  s27_1[2],
  s27_1[1],
  s27_1[0]};
assign n23 = s26_1 ? n20 : n19;
assign n24 = s26_1 ? n22 : n21;
cf_fft_2048_18_7 s25 (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);
cf_fft_2048_18_35 s26 (clock_c, n18, i4, i5, s26_1);
cf_fft_2048_18_31 s27 (clock_c, n2, n6, n11, n16, i4, i5, s27_1);
cf_fft_2048_18_30 s28 (clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3);
cf_fft_2048_18_26 s29 (clock_c, i1, i4, i5, s29_1, s29_2);
assign o3 = n24;
assign o2 = n23;
assign o1 = s28_1;
endmodule

module cf_fft_2048_18_7 (clock_c, i1, i2, i3, i4, i5, o1, o2);
input  clock_c;
input  [35:0] i1;
input  [35:0] i2;
input  i3;
input  i4;
input  i5;
output [35:0] o1;
output [35:0] o2;
reg    [35:0] n1;
wire   [17:0] n2;
wire   [17:0] n3;
reg    [35:0] n4;
wire   [17:0] n5;
wire   [17:0] n6;
reg    [17:0] n7;
reg    [17:0] n8;
reg    [17:0] n9;
reg    [17:0] n10;
reg    [35:0] n11;
wire   [17:0] n12;
wire   [17:0] n13;
wire   [35:0] n14;
wire   [17:0] n15;
reg    [17:0] n16;
wire   [35:0] n17;
wire   [17:0] n18;
reg    [17:0] n19;
wire   [17:0] n20;
reg    [17:0] n21;
wire   [35:0] n22;
wire   [17:0] n23;
reg    [17:0] n24;
wire   [35:0] n25;
wire   [17:0] n26;
reg    [17:0] n27;
wire   [17:0] n28;
reg    [17:0] n29;
wire   [17:0] n30;
wire   [17:0] n31;
wire   [35:0] n32;
reg    [35:0] n33;
wire   [17:0] n34;
wire   [17:0] n35;
wire   [35:0] n36;
reg    [35:0] n37;
initial n1 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n1 <= 36'b000000000000000000000000000000000000;
  else if (i4 == 1'b1)
    n1 <= i1;
assign n2 = {n1[35],
  n1[34],
  n1[33],
  n1[32],
  n1[31],
  n1[30],
  n1[29],
  n1[28],
  n1[27],
  n1[26],
  n1[25],
  n1[24],
  n1[23],
  n1[22],
  n1[21],
  n1[20],
  n1[19],
  n1[18]};
assign n3 = {n1[17],
  n1[16],
  n1[15],
  n1[14],
  n1[13],
  n1[12],
  n1[11],
  n1[10],
  n1[9],
  n1[8],
  n1[7],
  n1[6],
  n1[5],
  n1[4],
  n1[3],
  n1[2],
  n1[1],
  n1[0]};
initial n4 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n4 <= 36'b000000000000000000000000000000000000;
  else if (i4 == 1'b1)
    n4 <= i2;
assign n5 = {n4[35],
  n4[34],
  n4[33],
  n4[32],
  n4[31],
  n4[30],
  n4[29],
  n4[28],
  n4[27],
  n4[26],
  n4[25],
  n4[24],
  n4[23],
  n4[22],
  n4[21],
  n4[20],
  n4[19],
  n4[18]};
assign n6 = {n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
initial n7 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n7 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n7 <= n2;
initial n8 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n8 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n8 <= n7;
initial n9 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n9 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n9 <= n3;
initial n10 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n10 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n10 <= n9;
initial n11 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i4 == 1'b1)
    case (i3)
      1'b0 : n11 <= 36'b011111111111111111000000000000000000;
      1'b1 : n11 <= 36'b000000000000000000100000000000000000;
      default : n11 <= 36'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
    endcase
assign n12 = {n11[35],
  n11[34],
  n11[33],
  n11[32],
  n11[31],
  n11[30],
  n11[29],
  n11[28],
  n11[27],
  n11[26],
  n11[25],
  n11[24],
  n11[23],
  n11[22],
  n11[21],
  n11[20],
  n11[19],
  n11[18]};
assign n13 = {n11[17],
  n11[16],
  n11[15],
  n11[14],
  n11[13],
  n11[12],
  n11[11],
  n11[10],
  n11[9],
  n11[8],
  n11[7],
  n11[6],
  n11[5],
  n11[4],
  n11[3],
  n11[2],
  n11[1],
  n11[0]};
assign n14 = {{18{n5[17]}}, n5} * {{18{n12[17]}}, n12};
assign n15 = {n14[34],
  n14[33],
  n14[32],
  n14[31],
  n14[30],
  n14[29],
  n14[28],
  n14[27],
  n14[26],
  n14[25],
  n14[24],
  n14[23],
  n14[22],
  n14[21],
  n14[20],
  n14[19],
  n14[18],
  n14[17]};
initial n16 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n16 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n16 <= n15;
assign n17 = {{18{n6[17]}}, n6} * {{18{n13[17]}}, n13};
assign n18 = {n17[34],
  n17[33],
  n17[32],
  n17[31],
  n17[30],
  n17[29],
  n17[28],
  n17[27],
  n17[26],
  n17[25],
  n17[24],
  n17[23],
  n17[22],
  n17[21],
  n17[20],
  n17[19],
  n17[18],
  n17[17]};
initial n19 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n19 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n19 <= n18;
assign n20 = n16 - n19;
initial n21 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n21 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n21 <= n20;
assign n22 = {{18{n5[17]}}, n5} * {{18{n13[17]}}, n13};
assign n23 = {n22[34],
  n22[33],
  n22[32],
  n22[31],
  n22[30],
  n22[29],
  n22[28],
  n22[27],
  n22[26],
  n22[25],
  n22[24],
  n22[23],
  n22[22],
  n22[21],
  n22[20],
  n22[19],
  n22[18],
  n22[17]};
initial n24 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n24 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n24 <= n23;
assign n25 = {{18{n6[17]}}, n6} * {{18{n12[17]}}, n12};
assign n26 = {n25[34],
  n25[33],
  n25[32],
  n25[31],
  n25[30],
  n25[29],
  n25[28],
  n25[27],
  n25[26],
  n25[25],
  n25[24],
  n25[23],
  n25[22],
  n25[21],
  n25[20],
  n25[19],
  n25[18],
  n25[17]};
initial n27 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n27 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n27 <= n26;
assign n28 = n24 + n27;
initial n29 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n29 <= 18'b000000000000000000;
  else if (i4 == 1'b1)
    n29 <= n28;
assign n30 = n8 + n21;
assign n31 = n10 + n29;
assign n32 = {n30, n31};
initial n33 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n33 <= 36'b000000000000000000000000000000000000;
  else if (i4 == 1'b1)
    n33 <= n32;
assign n34 = n8 - n21;
assign n35 = n10 - n29;
assign n36 = {n34, n35};
initial n37 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i5 == 1'b1)
    n37 <= 36'b000000000000000000000000000000000000;
  else if (i4 == 1'b1)
    n37 <= n36;
assign o2 = n37;
assign o1 = n33;
endmodule

module cf_fft_2048_18_8 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);
input  clock_c;
input  i1;
input  [35:0] i2;
input  [35:0] i3;
input  i4;
input  i5;
output o1;