8051.cr.mti

利用verilog实现单片机的反向设计。编程环境为modelsim6.0

} {} {}} {F:/verilog experiment/8051core-Verilog/ram_wr_sel.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ ram_wr_sel\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(68):\ (vlog-2163)\ Macro\ `RWS_RN\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(68):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(69):\ (vlog-2163)\ Macro\ `RWS_I\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(70):\ (vlog-2163)\ Macro\ `RWS_D\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(71):\ (vlog-2163)\ Macro\ `RWS_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(72):\ (vlog-2163)\ Macro\ `RWS_ACC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(72):\ (vlog-2163)\ Macro\ `SFR_ACC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(73):\ (vlog-2163)\ Macro\ `RWS_D3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(74):\ (vlog-2163)\ Macro\ `RWS_DPTR\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(74):\ (vlog-2163)\ Macro\ `SFR_DPTR_LO\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(75):\ (vlog-2163)\ Macro\ `RWS_B\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/ram_wr_sel.v(75):\ (vlog-2163)\ Macro\ `SFR_B\ is\ undefined.\n\n {4.0 16.0} {}} {F:/verilog experiment/8051core-Verilog/Ram_sel.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/Ram_sel.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ ram_sel\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(73):\ (vlog-2163)\ Macro\ `SFR_ACC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(73):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(74):\ (vlog-2163)\ Macro\ `SFR_PSW\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(75):\ (vlog-2163)\ Macro\ `SFR_P0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(76):\ (vlog-2163)\ Macro\ `SFR_P1\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(77):\ (vlog-2163)\ Macro\ `SFR_P2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(78):\ (vlog-2163)\ Macro\ `SFR_P3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(79):\ (vlog-2163)\ Macro\ `SFR_DPTR_HI\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(90):\ (vlog-2163)\ Macro\ `SFR_B_ACC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(90):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(91):\ (vlog-2163)\ Macro\ `SFR_B_PSW\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(92):\ (vlog-2163)\ Macro\ `SFR_B_P0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(93):\ (vlog-2163)\ Macro\ `SFR_B_P1\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(94):\ (vlog-2163)\ Macro\ `SFR_B_P2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Ram_sel.v(95):\ (vlog-2163)\ Macro\ `SFR_B_P3\ is\ undefined.\n\n {4.0 19.0} {}} {F:/verilog experiment/8051core-Verilog/Port_out.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/Port_out.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ port_out\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(70):\ (vlog-2163)\ Macro\ `RST_P0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(70):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(71):\ (vlog-2163)\ Macro\ `RST_P1\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(71):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(72):\ (vlog-2163)\ Macro\ `RST_P2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(72):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(73):\ (vlog-2163)\ Macro\ `RST_P3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(73):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(80):\ (vlog-2163)\ Macro\ `SFR_P0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(80):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(81):\ (vlog-2163)\ Macro\ `SFR_P1\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(82):\ (vlog-2163)\ Macro\ `SFR_P2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(83):\ (vlog-2163)\ Macro\ `SFR_P3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(90):\ (vlog-2163)\ Macro\ `SFR_B_P0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(90):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(91):\ (vlog-2163)\ Macro\ `SFR_B_P1\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(92):\ (vlog-2163)\ Macro\ `SFR_B_P2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Port_out.v(93):\ (vlog-2163)\ Macro\ `SFR_B_P3\ is\ undefined.\n\n {4.0 22.0} {}} {F:/verilog experiment/8051core-Verilog/alu_src1_sel.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ alu_src1_sel\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v(64):\ (vlog-2163)\ Macro\ `ASS_RAM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v(64):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v(65):\ (vlog-2163)\ Macro\ `ASS_ACC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v(66):\ (vlog-2163)\ Macro\ `ASS_XRAM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/alu_src1_sel.v(67):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n\n {4.0 9.0} {}} {F:/verilog experiment/8051core-Verilog/Decoder.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/Decoder.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ decoder\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(107):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(107):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(108):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(108):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(109):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(109):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(110):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(110):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(111):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(111):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(113):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(113):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(114):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(114):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(115):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(115):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(116):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(116):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(117):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(117):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(119):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(119):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(120):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(120):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(121):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(121):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(122):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(122):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(127):\ (vlog-2163)\ Macro\ `ACALL\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(127):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(129):\ (vlog-2163)\ Macro\ `RWS_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(129):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(130):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(130):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(132):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(132):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(133):\ (vlog-2163)\ Macro\ `IDS_PCH\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(133):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(135):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(135):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(136):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(136):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(137):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(137):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(138):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(138):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(139):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(139):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(140):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(140):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(141):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(141):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(143):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(143):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(144):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(144):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(145):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(145):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(147):\ (vlog-2163)\ Macro\ `AJMP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(147):\ near\ \"begin\":\ syntax\ error,\ unexpected\ \"begin\",\ expecting\ \"IDENTIFIER\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(149):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(150):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(150):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(152):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(152):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(153):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(153):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(155):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(155):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(156):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(156):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(157):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(157):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(158):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(158):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(159):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(159):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(160):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(160):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(161):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(161):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(163):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(163):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(164):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(164):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(165):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(165):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(167):\ (vlog-2163)\ Macro\ `LCALL\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(167):\ near\ \"begin\":\ syntax\ error,\ unexpected\ \"begin\",\ expecting\ \"IDENTIFIER\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(169):\ (vlog-2163)\ Macro\ `RWS_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(169):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(170):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(170):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(172):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(172):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(173):\ (vlog-2163)\ Macro\ `IDS_PCH\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(173):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(175):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(175):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(176):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(176):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(177):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(177):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(178):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(178):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(179):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(179):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(180):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(180):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(181):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(181):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(183):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(183):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(184):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(184):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(185):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(185):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(187):\ near\ \"begin\":\ syntax\ error,\ unexpected\ \"begin\",\ expecting\ \"IDENTIFIER\"\ or\ \"clock\"\ or\ \"clocking\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(188):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(189):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(190):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(191):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(192):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(194):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(195):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(196):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(197):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(198):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(199):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(200):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(202):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(203):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(204):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(210):\ (vlog-2163)\ Macro\ `CJNE_R\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(211):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(212):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(213):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(214):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(215):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(217):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(218):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(220):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(221):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(222):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(223):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(225):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(226):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(227):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(229):\ (vlog-2163)\ Macro\ `CJNE_I\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(230):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(231):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(232):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(233):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(234):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(236):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(237):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(239):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(240):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(241):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(242):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(244):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(245):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(246):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(248):\ (vlog-2163)\ Macro\ `CJNE_D\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(249):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(250):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(251):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(252):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(253):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(255):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(256):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(258):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(259):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(260):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(261):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(263):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(264):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(265):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(267):\ (vlog-2163)\ Macro\ `CJNE_C\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(268):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(269):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(270):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(271):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(272):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(274):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(275):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(277):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(278):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(279):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(280):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(282):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(283):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(284):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(286):\ (vlog-2163)\ Macro\ `DJNZ_R\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(287):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(288):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(289):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(290):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(291):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(293):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(294):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(296):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(297):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(298):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(299):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(301):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(302):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(303):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(305):\ (vlog-2163)\ Macro\ `DJNZ_D\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(306):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(307):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(308):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(309):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(310):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(312):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(313):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(315):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(316):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(317):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(318):\ (vlog-2163)\ Macro\ `CSS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(320):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(321):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(322):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(324):\ (vlog-2163)\ Macro\ `JB\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(325):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(326):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(327):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(328):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(329):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(331):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(332):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(334):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(335):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(336):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(337):\ (vlog-2163)\ Macro\ `CSS_BIT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(339):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(340):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(341):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(343):\ (vlog-2163)\ Macro\ `JBC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(344):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(345):\ (vlog-2163)\ Macro\ `RWS_D\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(346):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(347):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(348):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(350):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(351):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(353):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(354):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(355):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(356):\ (vlog-2163)\ Macro\ `CSS_BIT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(358):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(359):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(360):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(362):\ (vlog-2163)\ Macro\ `JC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(363):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(364):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(365):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(366):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(367):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(369):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(370):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(372):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(373):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(374):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(375):\ (vlog-2163)\ Macro\ `CSS_CY\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(377):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(378):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(379):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(381):\ (vlog-2163)\ Macro\ `JMP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(382):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(383):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(384):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(385):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(386):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(388):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(389):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(390):\ (vlog-2163)\ Macro\ `PCW_Y\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(391):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(392):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(393):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(394):\ (vlog-2163)\ Macro\ `CSS_BIT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(396):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(397):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(398):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(400):\ (vlog-2163)\ Macro\ `JNB\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(401):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(402):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(403):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(404):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(405):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(407):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(408):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(410):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(411):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(412):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(413):\ (vlog-2163)\ Macro\ `CSS_BIT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(415):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(416):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(417):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(419):\ (vlog-2163)\ Macro\ `JNC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(420):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(421):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(422):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(423):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(424):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(426):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(427):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(429):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(430):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(431):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(432):\ (vlog-2163)\ Macro\ `CSS_CY\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(434):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(435):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(436):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(438):\ (vlog-2163)\ Macro\ `JNZ\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(439):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(440):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(441):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(442):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(443):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(445):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(446):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(448):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(449):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(450):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(451):\ (vlog-2163)\ Macro\ `CSS_AZ\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(453):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(454):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(455):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(457):\ (vlog-2163)\ Macro\ `JZ\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(458):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(459):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(460):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(461):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(462):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(464):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(465):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(467):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(468):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(469):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(470):\ (vlog-2163)\ Macro\ `CSS_AZ\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(472):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(473):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(474):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(476):\ (vlog-2163)\ Macro\ `MOVC_DP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(477):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(478):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(479):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(480):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(481):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(483):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(484):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(485):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(486):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(488):\ (vlog-2163)\ Macro\ `AS3_DP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(489):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(491):\ (vlog-2163)\ Macro\ `WAD_Y\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(492):\ (vlog-2163)\ Macro\ `RAS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(493):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(495):\ (vlog-2163)\ Macro\ `MOVC_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(496):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(497):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(498):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(499):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(500):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(502):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(503):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(504):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(505):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(507):\ (vlog-2163)\ Macro\ `AS3_DP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(508):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(510):\ (vlog-2163)\ Macro\ `WAD_Y\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(511):\ (vlog-2163)\ Macro\ `RAS_DES\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(512):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(514):\ (vlog-2163)\ Macro\ `SJMP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(515):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(516):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(517):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(518):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(519):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(521):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(522):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(523):\ (vlog-2163)\ Macro\ `PCW_Y\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(524):\ (vlog-2163)\ Macro\ `PIS_ALU\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(525):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(526):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(527):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(529):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(530):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(531):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(534):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(535):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(536):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(537):\ (vlog-2163)\ Macro\ `ASS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(538):\ (vlog-2163)\ Macro\ `ALU_NOP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(540):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(541):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(542):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(543):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(544):\ (vlog-2163)\ Macro\ `IDS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(545):\ (vlog-2163)\ Macro\ `AS3_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(546):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(548):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(549):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(550):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(556):\ (vlog-2163)\ Macro\ `CJNE_R\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(557):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(558):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(559):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(560):\ (vlog-2163)\ Macro\ `ASS_OP2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(561):\ (vlog-2163)\ Macro\ `ALU_PCS\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(563):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(564):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(565):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(566):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(567):\ (vlog-2163)\ Macro\ `IDS_OP3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(568):\ (vlog-2163)\ Macro\ `AS3_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(569):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(571):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(572):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(573):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(575):\ (vlog-2163)\ Macro\ `CJNE_I\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(576):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(577):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(578):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(579):\ (vlog-2163)\ Macro\ `ASS_OP2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(580):\ (vlog-2163)\ Macro\ `ALU_PCS\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(582):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(583):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(584):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(585):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(586):\ (vlog-2163)\ Macro\ `IDS_OP3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(587):\ (vlog-2163)\ Macro\ `AS3_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(588):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(590):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(591):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(592):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(594):\ (vlog-2163)\ Macro\ `CJNE_D\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(595):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(596):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(597):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(598):\ (vlog-2163)\ Macro\ `ASS_OP2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(599):\ (vlog-2163)\ Macro\ `ALU_PCS\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(601):\ (vlog-2163)\ Macro\ `PS_NOT\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(602):\ (vlog-2163)\ Macro\ `CY_0\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(603):\ (vlog-2163)\ Macro\ `PCW_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(604):\ (vlog-2163)\ Macro\ `PIS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(605):\ (vlog-2163)\ Macro\ `IDS_OP3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(606):\ (vlog-2163)\ Macro\ `AS3_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(607):\ (vlog-2163)\ Macro\ `CSS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(609):\ (vlog-2163)\ Macro\ `WAD_N\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(610):\ (vlog-2163)\ Macro\ `RAS_PC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(611):\ (vlog-2163)\ Macro\ `EAS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(613):\ (vlog-2163)\ Macro\ `CJNE_C\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(614):\ (vlog-2163)\ Macro\ `RRS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(615):\ (vlog-2163)\ Macro\ `RWS_DC\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(616):\ (vlog-2163)\ Macro\ `ASS_IMM\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(617):\ (vlog-2163)\ Macro\ `ASS_OP2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(618):\ (vlog-2163)\ Macro\ `ALU_PCS\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Decoder.v(620):\ (vlog-2163)\ Macro\ `PS_NOT\