8051.cr.mti

利用verilog实现单片机的反向设计。编程环境为modelsim6.0

	reg4

} {} {}} {F:/verilog experiment/8051core-Verilog/immediate_sel.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/immediate_sel.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ immediate_sel\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/immediate_sel.v(64):\ (vlog-2163)\ Macro\ `IDS_OP2\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/immediate_sel.v(64):\ near\ \":\":\ syntax\ error,\ unexpected\ ':',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/immediate_sel.v(65):\ (vlog-2163)\ Macro\ `IDS_OP3\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/immediate_sel.v(66):\ (vlog-2163)\ Macro\ `IDS_PCH\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/immediate_sel.v(67):\ (vlog-2163)\ Macro\ `IDS_PCL\ is\ undefined.\n\n {4.0 9.0} {}} {F:/verilog experiment/8051core-Verilog/Dptr.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/Dptr.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ dptr\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(71):\ (vlog-2163)\ Macro\ `RST_DPH\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(71):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(72):\ (vlog-2163)\ Macro\ `RST_DPL\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(72):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(73):\ (vlog-2163)\ Macro\ `RWS_DPTR\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(73):\ near\ \")\":\ syntax\ error,\ unexpected\ ')',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(78):\ near\ \"else\":\ syntax\ error,\ unexpected\ \"else\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(78):\ (vlog-2163)\ Macro\ `SFR_DPTR_HI\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Dptr.v(82):\ (vlog-2163)\ Macro\ `SFR_DPTR_LO\ is\ undefined.\n\n {4.0 13.0} {}} {F:/verilog experiment/8051core-Verilog/Sp.v} {0 vlog\ -work\ work\ -novopt\ \{F:/verilog\ experiment/8051core-Verilog/Sp.v\}\nModel\ Technology\ ModelSim\ SE\ vlog\ 6.1f\ Compiler\ 2006.05\ May\ 12\ 2006\n--\ Compiling\ module\ sp\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(72):\ (vlog-2163)\ Macro\ `RST_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(72):\ near\ \"\;\":\ syntax\ error,\ unexpected\ '\;',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(73):\ (vlog-2163)\ Macro\ `SFR_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(73):\ near\ \")\":\ syntax\ error,\ unexpected\ ')',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(81):\ (vlog-2163)\ Macro\ `RRS_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(81):\ near\ \")\":\ syntax\ error,\ unexpected\ ')',\ expecting\ \"'\{\"\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(88):\ (vlog-2163)\ Macro\ `RWS_SP\ is\ undefined.\n**\ Error:\ F:/verilog\ experiment/8051core-Verilog/Sp.v(88):\ near\ \")\":\ syntax\ error,\ unexpected\ ')',\ expecting\ \"'\{\"\n\n {4.0 12.0} {}} {F:/verilog experiment/8051core-Verilog/rom_addr_sel.v} {1 {vlog -work work -novopt {F:/verilog experiment/8051core-Verilog/rom_addr_sel.v}
Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006
-- Compiling module rom_addr_sel