count.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 10 行

module count(count_clk,con_out);
input count_clk;
output con_out;
reg con_out;
always@(posedge count_clk)
begin
	con_out=~con_out;
end
endmodule