📄 fre_test02.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 06 AND2 0 2 0 5 |lpm_add_sub:59|addcore:adder|:121
- 1 - B 12 AND2 0 4 0 3 |lpm_add_sub:59|addcore:adder|:133
- 4 - B 12 AND2 s ! 0 4 0 1 ~4~1
- 2 - B 12 AND2 0 4 0 5 :4
- 3 - B 12 DFFE + 0 3 0 1 count7 (:40)
- 5 - B 12 DFFE + 0 3 0 2 count6 (:41)
- 6 - B 12 DFFE + 0 2 0 3 count5 (:42)
- 7 - B 12 DFFE + 0 3 0 2 count4 (:43)
- 8 - B 12 DFFE + 0 2 0 3 count3 (:44)
- 1 - B 06 DFFE + 0 2 0 4 count2 (:45)
- 3 - B 06 DFFE + 0 2 0 1 count1 (:46)
- 4 - B 06 DFFE + 0 0 0 2 count0 (:47)
- 2 - B 06 DFFE + 0 1 1 0 :57
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test02.rpt
fre_test02
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test02.rpt
fre_test02
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test02.rpt
fre_test02
** EQUATIONS **
clk : INPUT;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC2_B6;
-- Node name is ':47' = 'count0'
-- Equation name is 'count0', location is LC4_B6, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':46' = 'count1'
-- Equation name is 'count1', location is LC3_B6, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !count1 & !_LC2_B12
# !count0 & count1 & !_LC2_B12;
-- Node name is ':45' = 'count2'
-- Equation name is 'count2', location is LC1_B6, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count2 & !_LC2_B12 & !_LC8_B6
# !count2 & !_LC2_B12 & _LC8_B6;
-- Node name is ':44' = 'count3'
-- Equation name is 'count3', location is LC8_B12, type is buried.
count3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !count2 & count3
# count3 & !_LC8_B6
# count2 & !count3 & _LC8_B6;
-- Node name is ':43' = 'count4'
-- Equation name is 'count4', location is LC7_B12, type is buried.
count4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !count2 & count4
# count4 & !_LC8_B6
# !count3 & count4
# count2 & count3 & !count4 & _LC8_B6;
-- Node name is ':42' = 'count5'
-- Equation name is 'count5', location is LC6_B12, type is buried.
count5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = count5 & !_LC1_B12 & !_LC2_B12
# !count5 & _LC1_B12 & !_LC2_B12;
-- Node name is ':41' = 'count6'
-- Equation name is 'count6', location is LC5_B12, type is buried.
count6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !count5 & count6 & !_LC2_B12
# count6 & !_LC1_B12 & !_LC2_B12
# count5 & !count6 & _LC1_B12 & !_LC2_B12;
-- Node name is ':40' = 'count7'
-- Equation name is 'count7', location is LC3_B12, type is buried.
count7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !count6 & count7
# !count5 & count7
# count7 & !_LC1_B12
# count5 & count6 & !count7 & _LC1_B12;
-- Node name is '|lpm_add_sub:59|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = LCELL( _EQ008);
_EQ008 = count0 & count1;
-- Node name is '|lpm_add_sub:59|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = LCELL( _EQ009);
_EQ009 = count2 & count3 & count4 & _LC8_B6;
-- Node name is '~4~1'
-- Equation name is '~4~1', location is LC4_B12, type is buried.
-- synthesized logic cell
!_LC4_B12 = _LC4_B12~NOT;
_LC4_B12~NOT = LCELL( _EQ010);
_EQ010 = !count4 & count5 & count6 & !count7;
-- Node name is ':4'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ011);
_EQ011 = !count2 & !count3 & !_LC4_B12 & _LC8_B6;
-- Node name is ':57'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = DFFE(!_LC2_B6, GLOBAL( clk), VCC, VCC, _LC2_B12);
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test02.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,111K
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