📄 phaseme.rpt
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-- Node name is '|fre_div:11|:212' = '|fre_div:11|count4'
-- Equation name is '_LC7_C10', type is buried
_LC7_C10 = DFFE( _EQ069, bin, VCC, VCC, VCC);
_EQ069 = !_LC4_C15 & _LC5_C10 & _LC6_C10 & !_LC7_C10
# !_LC4_C15 & !_LC6_C10 & _LC7_C10
# !_LC4_C15 & !_LC5_C10 & _LC7_C10;
-- Node name is '|fre_div:11|:211' = '|fre_div:11|count5'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = DFFE( _EQ070, bin, VCC, VCC, VCC);
_EQ070 = !_LC6_C12 & _LC8_C10
# _LC4_C15 & _LC8_C10
# !_LC4_C15 & _LC6_C12 & !_LC8_C10;
-- Node name is '|fre_div:11|:210' = '|fre_div:11|count6'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = DFFE( _EQ071, bin, VCC, VCC, VCC);
_EQ071 = !_LC4_C15 & _LC6_C12 & !_LC7_C12 & _LC8_C10
# !_LC4_C15 & !_LC6_C12 & _LC7_C12
# !_LC4_C15 & _LC7_C12 & !_LC8_C10;
-- Node name is '|fre_div:11|:209' = '|fre_div:11|count7'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = DFFE( _EQ072, bin, VCC, VCC, VCC);
_EQ072 = !_LC1_C20 & _LC3_C12
# _LC3_C12 & _LC4_C15
# _LC1_C20 & !_LC3_C12 & !_LC4_C15;
-- Node name is '|fre_div:11|:208' = '|fre_div:11|count8'
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = DFFE( _EQ073, bin, VCC, VCC, VCC);
_EQ073 = _LC1_C20 & _LC3_C12 & !_LC3_C20 & !_LC4_C15
# !_LC1_C20 & _LC3_C20 & !_LC4_C15
# !_LC3_C12 & _LC3_C20 & !_LC4_C15;
-- Node name is '|fre_div:11|:207' = '|fre_div:11|count9'
-- Equation name is '_LC5_C20', type is buried
_LC5_C20 = DFFE( _EQ074, bin, VCC, VCC, VCC);
_EQ074 = _LC4_C20 & !_LC5_C20
# _LC4_C15 & _LC4_C20
# !_LC4_C15 & !_LC4_C20 & _LC5_C20;
-- Node name is '|fre_div:11|:206' = '|fre_div:11|count10'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = DFFE( _EQ075, bin, VCC, VCC, VCC);
_EQ075 = !_LC4_C15 & _LC4_C20 & _LC5_C20 & !_LC6_C20
# !_LC4_C15 & !_LC5_C20 & _LC6_C20
# !_LC4_C15 & !_LC4_C20 & _LC6_C20;
-- Node name is '|fre_div:11|:205' = '|fre_div:11|count11'
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = DFFE( _EQ076, bin, VCC, VCC, VCC);
_EQ076 = _LC2_C20 & !_LC7_C20
# _LC2_C20 & _LC4_C15
# !_LC2_C20 & !_LC4_C15 & _LC7_C20;
-- Node name is '|fre_div:11|:204' = '|fre_div:11|count12'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = DFFE( _EQ077, bin, VCC, VCC, VCC);
_EQ077 = _LC2_C20 & !_LC3_C15 & !_LC4_C15 & _LC7_C20
# _LC3_C15 & !_LC4_C15 & !_LC7_C20
# !_LC2_C20 & _LC3_C15 & !_LC4_C15;
-- Node name is '|fre_div:11|:203' = '|fre_div:11|count13'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = DFFE( _EQ078, bin, VCC, VCC, VCC);
_EQ078 = _LC5_C15 & !_LC6_C15
# _LC4_C15 & _LC5_C15
# !_LC4_C15 & !_LC5_C15 & _LC6_C15;
-- Node name is '|fre_div:11|:202' = '|fre_div:11|count14'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = DFFE( _EQ079, bin, VCC, VCC, VCC);
_EQ079 = !_LC4_C15 & _LC5_C15 & _LC6_C15 & !_LC8_C15
# !_LC4_C15 & !_LC6_C15 & _LC8_C15
# !_LC4_C15 & !_LC5_C15 & _LC8_C15;
-- Node name is '|fre_div:11|:201' = '|fre_div:11|count15'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = DFFE( _EQ080, bin, VCC, VCC, VCC);
_EQ080 = !_LC4_C15 & _LC5_C15 & _LC6_C15 & _LC8_C15;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C10', type is buried
_LC5_C10 = LCELL( _EQ081);
_EQ081 = _LC2_C12 & _LC3_C10 & _LC4_C12 & !_LC4_C15;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C10', type is buried
_LC8_C10 = LCELL( _EQ082);
_EQ082 = !_LC4_C15 & _LC5_C10 & _LC6_C10 & _LC7_C10;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = LCELL( _EQ083);
_EQ083 = !_LC4_C15 & _LC6_C12 & _LC7_C12 & _LC8_C10;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ084);
_EQ084 = _LC1_C20 & _LC3_C12 & _LC3_C20 & !_LC4_C15;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ085);
_EQ085 = !_LC4_C15 & _LC4_C20 & _LC5_C20 & _LC6_C20;
-- Node name is '|fre_div:11|lpm_add_sub:225|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = LCELL( _EQ086);
_EQ086 = _LC2_C20 & _LC3_C15 & !_LC4_C15 & _LC7_C20;
-- Node name is '|fre_div:11|:41'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ087);
_EQ087 = _LC7_C15
# _LC2_C15 & _LC8_C15
# !_LC1_C17 & _LC2_C15
# !_LC1_C17 & _LC8_C15;
-- Node name is '|fre_div:11|:51'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ088);
_EQ088 = _LC1_C15 & _LC6_C15
# _LC1_C15 & !_LC5_C16
# !_LC5_C16 & _LC6_C15;
-- Node name is '|fre_div:11|:56'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = LCELL( _EQ089);
_EQ089 = _LC3_C15 & _LC4_C24
# _LC4_C24 & !_LC6_C16
# _LC3_C15 & !_LC6_C16;
-- Node name is '|fre_div:11|:61'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = LCELL( _EQ090);
_EQ090 = _LC3_C24 & _LC7_C20
# _LC3_C24 & !_LC7_C24
# _LC7_C20 & !_LC7_C24;
-- Node name is '|fre_div:11|:66'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = LCELL( _EQ091);
_EQ091 = _LC2_C24 & _LC6_C20
# _LC2_C24 & !_LC3_C18
# !_LC3_C18 & _LC6_C20;
-- Node name is '|fre_div:11|:71'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = LCELL( _EQ092);
_EQ092 = _LC1_C24 & _LC5_C20
# !_LC1_C14 & _LC1_C24
# !_LC1_C14 & _LC5_C20;
-- Node name is '|fre_div:11|:76'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ093);
_EQ093 = _LC3_C20 & _LC8_C20
# !_LC6_C18 & _LC8_C20
# _LC3_C20 & !_LC6_C18;
-- Node name is '|fre_div:11|:81'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = LCELL( _EQ094);
_EQ094 = _LC1_C20 & _LC8_C12
# _LC8_C12 & !_LC8_C21
# _LC1_C20 & !_LC8_C21;
-- Node name is '|fre_div:11|:86'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ095);
_EQ095 = _LC5_C12 & _LC7_C12
# _LC5_C12 & !_LC5_C17
# !_LC5_C17 & _LC7_C12;
-- Node name is '|fre_div:11|:91'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ096);
_EQ096 = _LC4_C10 & _LC6_C12
# !_LC3_C16 & _LC4_C10
# !_LC3_C16 & _LC6_C12;
-- Node name is '|fre_div:11|:96'
-- Equation name is '_LC4_C10', type is buried
_LC4_C10 = LCELL( _EQ097);
_EQ097 = _LC2_C10 & _LC7_C10
# _LC2_C10 & !_LC4_C21
# !_LC4_C21 & _LC7_C10;
-- Node name is '|fre_div:11|:101'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = LCELL( _EQ098);
_EQ098 = _LC1_C10 & _LC6_C10
# _LC1_C10 & !_LC7_C21
# _LC6_C10 & !_LC7_C21;
-- Node name is '|fre_div:11|:106'
-- Equation name is '_LC1_C10', type is buried
_LC1_C10 = LCELL( _EQ099);
_EQ099 = _LC1_C12 & _LC3_C10
# _LC1_C12 & !_LC5_C18
# _LC3_C10 & !_LC5_C18;
-- Node name is '|fre_div:11|:111'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ100);
_EQ100 = !_LC1_C16 & _LC2_C12
# !_LC1_C18 & _LC2_C12 & _LC4_C12
# !_LC1_C16 & !_LC1_C18 & _LC4_C12;
-- Node name is '|fre_div:11|:224'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = DFFE( _EQ101, bin, VCC, VCC, VCC);
_EQ101 = _LC2_C4 & !_LC4_C15
# !_LC2_C4 & _LC4_C15;
-- Node name is ':16'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ102);
_EQ102 = !_LC2_C4 & _LC4_C23
# _LC2_C4 & !_LC4_C23;
-- Node name is ':23'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ103);
_EQ103 = _LC2_C4 & _LC4_C23
# !_LC2_C4 & !_LC4_C23
# !_LC2_A10;
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
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