📄 phaseme.rpt
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Total: 0 0 0 4 0 0 0 0 0 9 0 8 0 8 7 8 13 5 8 8 8 8 8 4 16 122/0
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
72 - - - 04 INPUT 0 0 0 17 ain
73 - - - 02 INPUT 0 0 0 17 bin
55 - - - -- INPUT G 0 0 0 0 clk
8 - - A -- INPUT 0 0 0 1 datain0
9 - - A -- INPUT 0 0 0 3 datain1
10 - - A -- INPUT 0 0 0 3 datain2
12 - - A -- INPUT 0 0 0 3 datain3
13 - - A -- INPUT 0 0 0 3 datain4
17 - - B -- INPUT 0 0 0 3 datain5
18 - - B -- INPUT 0 0 0 3 datain6
19 - - B -- INPUT 0 0 0 3 datain7
20 - - B -- INPUT 0 0 0 26 trans
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - C -- OUTPUT 0 1 0 0 afreout
81 - - C -- OUTPUT 0 1 0 0 bfreout
32 - - C -- OUTPUT 0 1 0 0 conf_out
21 - - B -- OUTPUT 0 1 0 0 con_out
22 - - B -- OUTPUT 0 1 0 0 freout
82 - - C -- OUTPUT 0 1 0 0 out36
90 - - B -- OUTPUT 0 1 0 0 p
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 04 DFFE 0 1 1 0 |count:5|:5
- 3 - C 17 DFFE 1 0 0 25 |div_quan:7|datahorl_flag (|div_quan:7|:42)
- 7 - C 17 DFFE 1 1 1 0 |div_quan:7|:46
- 2 - C 17 DFFE 2 1 0 2 |div_quan:7|outhelp15 (|div_quan:7|:145)
- 7 - C 16 DFFE 2 1 0 2 |div_quan:7|outhelp14 (|div_quan:7|:146)
- 2 - C 16 DFFE 2 1 0 2 |div_quan:7|outhelp13 (|div_quan:7|:147)
- 5 - C 24 DFFE 2 1 0 2 |div_quan:7|outhelp12 (|div_quan:7|:148)
- 2 - C 18 DFFE 2 1 0 2 |div_quan:7|outhelp11 (|div_quan:7|:149)
- 4 - C 16 DFFE 2 1 0 2 |div_quan:7|outhelp10 (|div_quan:7|:150)
- 7 - C 18 DFFE 2 1 0 2 |div_quan:7|outhelp9 (|div_quan:7|:151)
- 2 - C 21 DFFE 2 1 0 2 |div_quan:7|outhelp8 (|div_quan:7|:152)
- 1 - C 17 DFFE 1 2 0 2 |div_quan:7|:227
- 5 - C 16 DFFE 1 2 0 2 |div_quan:7|:228
- 6 - C 16 DFFE 1 2 0 2 |div_quan:7|:229
- 7 - C 24 DFFE 1 2 0 2 |div_quan:7|:230
- 3 - C 18 DFFE 1 2 0 2 |div_quan:7|:231
- 1 - C 14 DFFE 1 2 0 2 |div_quan:7|:232
- 6 - C 18 DFFE 1 2 0 2 |div_quan:7|:233
- 8 - C 21 DFFE 1 2 0 2 |div_quan:7|:234
- 5 - C 17 DFFE 2 1 0 2 |div_quan:7|:235
- 3 - C 16 DFFE 2 1 0 2 |div_quan:7|:236
- 4 - C 21 DFFE 2 1 0 2 |div_quan:7|:237
- 7 - C 21 DFFE 2 1 0 2 |div_quan:7|:238
- 5 - C 18 DFFE 2 1 0 2 |div_quan:7|:239
- 1 - C 16 DFFE 2 1 0 2 |div_quan:7|:240
- 1 - C 18 DFFE 2 1 0 2 |div_quan:7|:241
- 8 - C 16 AND2 s 0 4 0 1 |div_quan:7|~273~1
- 3 - C 21 AND2 s 3 0 0 1 |div_quan:7|~273~2
- 5 - C 21 AND2 s 3 0 0 1 |div_quan:7|~273~3
- 6 - C 21 AND2 s 1 3 0 1 |div_quan:7|~273~4
- 8 - C 18 AND2 s 0 4 0 1 |div_quan:7|~273~5
- 4 - C 18 DFFE 1 3 1 0 |div_quan:7|:297
- 1 - A 24 AND2 0 4 0 4 |div_36k:6|lpm_add_sub:52|addcore:adder|:125
- 1 - A 16 AND2 0 4 0 2 |div_36k:6|lpm_add_sub:52|addcore:adder|:137
- 2 - A 16 AND2 s ! 0 3 0 2 |div_36k:6|~4~1
- 4 - A 24 AND2 s ! 0 3 0 2 |div_36k:6|~4~2
- 3 - A 24 AND2 0 4 0 6 |div_36k:6|:4
- 5 - A 24 DFFE + 0 3 0 1 |div_36k:6|count_36k7 (|div_36k:6|:41)
- 7 - A 24 DFFE + 0 1 0 2 |div_36k:6|count_36k6 (|div_36k:6|:42)
- 3 - A 16 DFFE + 0 3 0 3 |div_36k:6|count_36k5 (|div_36k:6|:43)
- 4 - A 16 DFFE + 0 2 0 3 |div_36k:6|count_36k4 (|div_36k:6|:44)
- 5 - A 16 DFFE + 0 2 0 4 |div_36k:6|count_36k3 (|div_36k:6|:45)
- 2 - A 24 DFFE + 0 3 0 2 |div_36k:6|count_36k2 (|div_36k:6|:46)
- 6 - A 24 DFFE + 0 2 0 3 |div_36k:6|count_36k1 (|div_36k:6|:47)
- 8 - A 24 DFFE + 0 3 0 4 |div_36k:6|count_36k0 (|div_36k:6|:48)
- 2 - A 10 DFFE + 0 1 1 1 |div_36k:6|:50
- 8 - C 19 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:107
- 4 - C 19 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:115
- 1 - C 22 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:123
- 6 - C 22 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:131
- 4 - C 22 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:139
- 4 - C 13 AND2 0 4 0 3 |fre_div:8|lpm_add_sub:225|addcore:adder|:147
- 8 - C 13 OR2 0 4 0 23 |fre_div:8|:41
- 2 - C 13 OR2 0 3 0 1 |fre_div:8|:51
- 1 - C 13 OR2 0 3 0 1 |fre_div:8|:56
- 8 - C 24 OR2 0 3 0 1 |fre_div:8|:61
- 6 - C 24 OR2 0 3 0 1 |fre_div:8|:66
- 6 - C 14 OR2 0 3 0 1 |fre_div:8|:71
- 7 - C 14 OR2 0 3 0 1 |fre_div:8|:76
- 5 - C 14 OR2 0 3 0 1 |fre_div:8|:81
- 4 - C 14 OR2 0 3 0 1 |fre_div:8|:86
- 3 - C 14 OR2 0 3 0 1 |fre_div:8|:91
- 2 - C 14 OR2 0 3 0 1 |fre_div:8|:96
- 1 - C 21 OR2 0 3 0 1 |fre_div:8|:101
- 1 - C 19 OR2 0 3 0 1 |fre_div:8|:106
- 3 - C 19 OR2 0 4 0 1 |fre_div:8|:111
- 6 - C 13 DFFE 1 4 0 1 |fre_div:8|count15 (|fre_div:8|:201)
- 7 - C 13 DFFE 1 3 0 2 |fre_div:8|count14 (|fre_div:8|:202)
- 5 - C 13 DFFE 1 2 0 3 |fre_div:8|count13 (|fre_div:8|:203)
- 3 - C 13 DFFE 1 3 0 2 |fre_div:8|count12 (|fre_div:8|:204)
- 1 - C 23 DFFE 1 2 0 3 |fre_div:8|count11 (|fre_div:8|:205)
- 5 - C 22 DFFE 1 3 0 2 |fre_div:8|count10 (|fre_div:8|:206)
- 8 - C 22 DFFE 1 2 0 3 |fre_div:8|count9 (|fre_div:8|:207)
- 3 - C 22 DFFE 1 3 0 2 |fre_div:8|count8 (|fre_div:8|:208)
- 7 - C 22 DFFE 1 2 0 3 |fre_div:8|count7 (|fre_div:8|:209)
- 2 - C 22 DFFE 1 3 0 2 |fre_div:8|count6 (|fre_div:8|:210)
- 3 - C 23 DFFE 1 2 0 3 |fre_div:8|count5 (|fre_div:8|:211)
- 2 - C 19 DFFE 1 3 0 2 |fre_div:8|count4 (|fre_div:8|:212)
- 6 - C 19 DFFE 1 2 0 3 |fre_div:8|count3 (|fre_div:8|:213)
- 7 - C 19 DFFE 1 3 0 2 |fre_div:8|count2 (|fre_div:8|:214)
- 5 - C 19 DFFE 1 2 0 3 |fre_div:8|count1 (|fre_div:8|:215)
- 5 - C 23 DFFE 1 1 0 4 |fre_div:8|count0 (|fre_div:8|:216)
- 4 - C 23 DFFE 1 1 1 2 |fre_div:8|:224
- 5 - C 10 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:107
- 8 - C 10 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:115
- 3 - C 12 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:123
- 4 - C 20 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:131
- 2 - C 20 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:139
- 5 - C 15 AND2 0 4 0 3 |fre_div:11|lpm_add_sub:225|addcore:adder|:147
- 4 - C 15 OR2 0 4 0 23 |fre_div:11|:41
- 2 - C 15 OR2 0 3 0 1 |fre_div:11|:51
- 1 - C 15 OR2 0 3 0 1 |fre_div:11|:56
- 4 - C 24 OR2 0 3 0 1 |fre_div:11|:61
- 3 - C 24 OR2 0 3 0 1 |fre_div:11|:66
- 2 - C 24 OR2 0 3 0 1 |fre_div:11|:71
- 1 - C 24 OR2 0 3 0 1 |fre_div:11|:76
- 8 - C 20 OR2 0 3 0 1 |fre_div:11|:81
- 8 - C 12 OR2 0 3 0 1 |fre_div:11|:86
- 5 - C 12 OR2 0 3 0 1 |fre_div:11|:91
- 4 - C 10 OR2 0 3 0 1 |fre_div:11|:96
- 2 - C 10 OR2 0 3 0 1 |fre_div:11|:101
- 1 - C 10 OR2 0 3 0 1 |fre_div:11|:106
- 1 - C 12 OR2 0 4 0 1 |fre_div:11|:111
- 7 - C 15 DFFE 1 4 0 1 |fre_div:11|count15 (|fre_div:11|:201)
- 8 - C 15 DFFE 1 3 0 2 |fre_div:11|count14 (|fre_div:11|:202)
- 6 - C 15 DFFE 1 2 0 3 |fre_div:11|count13 (|fre_div:11|:203)
- 3 - C 15 DFFE 1 3 0 2 |fre_div:11|count12 (|fre_div:11|:204)
- 7 - C 20 DFFE 1 2 0 3 |fre_div:11|count11 (|fre_div:11|:205)
- 6 - C 20 DFFE 1 3 0 2 |fre_div:11|count10 (|fre_div:11|:206)
- 5 - C 20 DFFE 1 2 0 3 |fre_div:11|count9 (|fre_div:11|:207)
- 3 - C 20 DFFE 1 3 0 2 |fre_div:11|count8 (|fre_div:11|:208)
- 1 - C 20 DFFE 1 2 0 3 |fre_div:11|count7 (|fre_div:11|:209)
- 7 - C 12 DFFE 1 3 0 2 |fre_div:11|count6 (|fre_div:11|:210)
- 6 - C 12 DFFE 1 2 0 3 |fre_div:11|count5 (|fre_div:11|:211)
- 7 - C 10 DFFE 1 3 0 2 |fre_div:11|count4 (|fre_div:11|:212)
- 6 - C 10 DFFE 1 2 0 3 |fre_div:11|count3 (|fre_div:11|:213)
- 3 - C 10 DFFE 1 3 0 2 |fre_div:11|count2 (|fre_div:11|:214)
- 2 - C 12 DFFE 1 2 0 3 |fre_div:11|count1 (|fre_div:11|:215)
- 4 - C 12 DFFE 1 1 0 4 |fre_div:11|count0 (|fre_div:11|:216)
- 2 - C 04 DFFE 1 1 1 2 |fre_div:11|:224
- 1 - C 04 OR2 0 2 0 1 :16
- 6 - C 04 OR2 0 3 1 0 :23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 5/ 48( 10%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
C: 23/ 96( 23%) 9/ 48( 18%) 40/ 48( 83%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 trans
INPUT 17 ain
INPUT 17 bin
INPUT 9 clk
LCELL 1 :16
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\phaseme.rpt
phaseme
** EQUATIONS **
ain : INPUT;
bin : INPUT;
clk : INPUT;
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