fre_test02.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 16 行

module fre_test02(clk,clkout);
input clk;
output clkout;
reg clkout;
reg[7:0] count;
always@(posedge clk)
begin
	count=count+1;
	if(count==100)
	begin
		clkout=~clkout;
		count=0;
	end
end
endmodule