div_36k.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 16 行

module div_36k(clk,clk_out);
input clk;
output clk_out;
reg clk_out;
reg[7:0] count_36k;
always@(posedge clk)
begin
	if(count_36k==139)
	begin
		clk_out=~clk_out;
		count_36k=0;
	end
count_36k=count_36k+1;
end
endmodule