📄 div_quan.rpt
字号:
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC30 dataout6
| +----------------------------- LC31 dataout8
| | +--------------------------- LC32 dataout9
| | | +------------------------- LC28 dataout10
| | | | +----------------------- LC21 dataout11
| | | | | +--------------------- LC18 dataout12
| | | | | | +------------------- LC22 dataout13
| | | | | | | +----------------- LC19 dataout14
| | | | | | | | +--------------- LC17 p
| | | | | | | | | +------------- LC23 outhelp15
| | | | | | | | | | +----------- LC24 outhelp14
| | | | | | | | | | | +--------- LC25 outhelp13
| | | | | | | | | | | | +------- LC29 outhelp12
| | | | | | | | | | | | | +----- LC20 outhelp11
| | | | | | | | | | | | | | +--- LC26 outhelp10
| | | | | | | | | | | | | | | +- LC27 outhelp9
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - - - - - - - - * - - - - - - - | - * | <-- p
LC23 -> - - - - - - - * * * - - - - - - | - * | <-- outhelp15
LC24 -> - - - - - - * - * - * - - - - - | - * | <-- outhelp14
LC25 -> - - - - - * - - * - - * - - - - | - * | <-- outhelp13
LC29 -> - - - - * - - - * - - - * - - - | - * | <-- outhelp12
LC20 -> - - - * - - - - * - - - - * - - | - * | <-- outhelp11
LC26 -> - - * - - - - - * - - - - - * - | - * | <-- outhelp10
LC27 -> - * - - - - - - * - - - - - - * | - * | <-- outhelp9
Pin
4 -> - * - - - - - - * - - - - - - * | * * | <-- datain1
5 -> - - * - - - - - * - - - - - * - | * * | <-- datain2
34 -> - - - * - - - - * - - - - * - - | * * | <-- datain3
33 -> - - - - * - - - * - - - * - - - | * * | <-- datain4
31 -> - - - - - * - - * - - * - - - - | * * | <-- datain5
11 -> - - - - - - * - * - * - - - - - | * * | <-- datain6
12 -> * - - - - - - * * * - - - - - - | - * | <-- datain7
43 -> - - - - - - - - - - - - - - - - | - - | <-- trans
LC1 -> * * * * * * * * * * * * * * * * | * * | <-- datahorl_flag
LC2 -> - - - - - - - - * - - - - - - - | * * | <-- outhelp8
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** EQUATIONS **
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
datain4 : INPUT;
datain5 : INPUT;
datain6 : INPUT;
datain7 : INPUT;
trans : INPUT;
-- Node name is 'con_count' = ':46'
-- Equation name is 'con_count', type is output
con_count = DFFE(!datahorl_flag $ GND, GLOBAL( trans), VCC, VCC, VCC);
-- Node name is ':42' = 'datahorl_flag'
-- Equation name is 'datahorl_flag', location is LC001, type is buried.
datahorl_flag = TFFE( VCC, GLOBAL( trans), VCC, VCC, VCC);
-- Node name is 'dataout0' = ':241'
-- Equation name is 'dataout0', type is output
dataout0 = DFFE( datain1 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout1' = ':240'
-- Equation name is 'dataout1', type is output
dataout1 = DFFE( datain2 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout2' = ':239'
-- Equation name is 'dataout2', type is output
dataout2 = DFFE( datain3 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout3' = ':238'
-- Equation name is 'dataout3', type is output
dataout3 = DFFE( datain4 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout4' = ':237'
-- Equation name is 'dataout4', type is output
dataout4 = DFFE( datain5 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout5' = ':236'
-- Equation name is 'dataout5', type is output
dataout5 = DFFE( datain6 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout6' = ':235'
-- Equation name is 'dataout6', type is output
dataout6 = DFFE( datain7 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
-- Node name is 'dataout7' = ':234'
-- Equation name is 'dataout7', type is output
dataout7 = DFFE( _EQ001 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ001 = datahorl_flag & outhelp8
# !datahorl_flag & datain0;
-- Node name is 'dataout8' = ':233'
-- Equation name is 'dataout8', type is output
dataout8 = DFFE( _EQ002 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ002 = datahorl_flag & outhelp9
# !datahorl_flag & datain1;
-- Node name is 'dataout9' = ':232'
-- Equation name is 'dataout9', type is output
dataout9 = DFFE( _EQ003 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ003 = datahorl_flag & outhelp10
# !datahorl_flag & datain2;
-- Node name is 'dataout10' = ':231'
-- Equation name is 'dataout10', type is output
dataout10 = DFFE( _EQ004 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ004 = datahorl_flag & outhelp11
# !datahorl_flag & datain3;
-- Node name is 'dataout11' = ':230'
-- Equation name is 'dataout11', type is output
dataout11 = DFFE( _EQ005 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ005 = datahorl_flag & outhelp12
# !datahorl_flag & datain4;
-- Node name is 'dataout12' = ':229'
-- Equation name is 'dataout12', type is output
dataout12 = DFFE( _EQ006 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ006 = datahorl_flag & outhelp13
# !datahorl_flag & datain5;
-- Node name is 'dataout13' = ':228'
-- Equation name is 'dataout13', type is output
dataout13 = DFFE( _EQ007 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ007 = datahorl_flag & outhelp14
# !datahorl_flag & datain6;
-- Node name is 'dataout14' = ':227'
-- Equation name is 'dataout14', type is output
dataout14 = DFFE( _EQ008 $ GND, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ008 = datahorl_flag & outhelp15
# !datahorl_flag & datain7;
-- Node name is 'dataout15'
-- Equation name is 'dataout15', location is LC011, type is output.
dataout15 = LCELL( GND $ GND);
-- Node name is ':152' = 'outhelp8'
-- Equation name is 'outhelp8', location is LC002, type is buried.
outhelp8 = DFFE( _EQ009 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ009 = datahorl_flag & outhelp8
# !datahorl_flag & datain0;
-- Node name is ':151' = 'outhelp9'
-- Equation name is 'outhelp9', location is LC027, type is buried.
outhelp9 = DFFE( _EQ010 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ010 = datahorl_flag & outhelp9
# !datahorl_flag & datain1;
-- Node name is ':150' = 'outhelp10'
-- Equation name is 'outhelp10', location is LC026, type is buried.
outhelp10 = DFFE( _EQ011 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ011 = datahorl_flag & outhelp10
# !datahorl_flag & datain2;
-- Node name is ':149' = 'outhelp11'
-- Equation name is 'outhelp11', location is LC020, type is buried.
outhelp11 = DFFE( _EQ012 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ012 = datahorl_flag & outhelp11
# !datahorl_flag & datain3;
-- Node name is ':148' = 'outhelp12'
-- Equation name is 'outhelp12', location is LC029, type is buried.
outhelp12 = DFFE( _EQ013 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ013 = datahorl_flag & outhelp12
# !datahorl_flag & datain4;
-- Node name is ':147' = 'outhelp13'
-- Equation name is 'outhelp13', location is LC025, type is buried.
outhelp13 = DFFE( _EQ014 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ014 = datahorl_flag & outhelp13
# !datahorl_flag & datain5;
-- Node name is ':146' = 'outhelp14'
-- Equation name is 'outhelp14', location is LC024, type is buried.
outhelp14 = DFFE( _EQ015 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ015 = datahorl_flag & outhelp14
# !datahorl_flag & datain6;
-- Node name is ':145' = 'outhelp15'
-- Equation name is 'outhelp15', location is LC023, type is buried.
outhelp15 = DFFE( _EQ016 $ GND, GLOBAL( trans), VCC, VCC, VCC);
_EQ016 = datahorl_flag & outhelp15
# !datahorl_flag & datain7;
-- Node name is 'p' = ':297'
-- Equation name is 'p', type is output
p = TFFE( _EQ017, GLOBAL( trans), VCC, VCC, datahorl_flag);
_EQ017 = datahorl_flag & !datain1 & !datain2 & !datain3 & datain4 &
!datain5 & !datain6 & !datain7 & outhelp8 & outhelp9 &
outhelp10 & !outhelp11 & !outhelp12 & outhelp13 & !outhelp14 &
!outhelp15 & !p;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,279K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -