📄 div_quan.rpt
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Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 08/27/2005 10:27:29
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
div_quan EPM7032SLC44-5 9 18 0 27 0 84 %
User Pins: 9 18 0
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':226' stuck at GND
Warning: Primitive 'dataout15' is stuck at GND
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'trans' chosen for auto global Clock
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
***** Logic for device 'div_quan' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
d
d a
a d d t
t a a a
a t t t o
o a a r u
u i i V G G G a G t
t n n C N N N n N 1
5 2 1 C D D D s D p 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | dataout14
dataout1 | 8 38 | #TDO
dataout0 | 9 37 | dataout11
GND | 10 36 | dataout13
datain6 | 11 35 | VCC
datain7 | 12 EPM7032SLC44-5 34 | datain3
#TMS | 13 33 | datain4
datain0 | 14 32 | #TCK
VCC | 15 31 | datain5
dataout15 | 16 30 | GND
con_count | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
d d d d G V d d d R d
a a a a N C a a a E a
t t t t D C t t t S t
a a a a a a a E a
o o o o o o o R o
u u u u u u u V u
t t t t t t t E t
4 3 7 2 9 8 6 D 1
0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 11/16( 68%) 16/16(100%) 0/16( 0%) 9/36( 25%)
B: LC17 - LC32 16/16(100%) 14/16( 87%) 0/16( 0%) 17/36( 47%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 30/32 ( 93%)
Total logic cells used: 27/32 ( 84%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 27/32 ( 84%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 3.96
Total fan-in: 107
Total input pins required: 9
Total fast input logic cells required: 0
Total output pins required: 18
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 27
Total flipflops required: 26
Total product terms required: 59
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (10) (A) INPUT 0 0 0 0 0 1 1 datain0
4 (1) (A) INPUT 0 0 0 0 0 3 1 datain1
5 (2) (A) INPUT 0 0 0 0 0 3 1 datain2
34 (23) (B) INPUT 0 0 0 0 0 3 1 datain3
33 (24) (B) INPUT 0 0 0 0 0 3 1 datain4
31 (26) (B) INPUT 0 0 0 0 0 3 1 datain5
11 (7) (A) INPUT 0 0 0 0 0 3 1 datain6
12 (8) (A) INPUT 0 0 0 0 0 3 1 datain7
43 - - INPUT G 0 0 0 0 0 0 0 trans
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 12 A FF + t 0 0 0 0 1 0 0 con_count
9 6 A FF + t 0 0 0 1 1 0 0 dataout0
8 5 A FF + t 0 0 0 1 1 0 0 dataout1
21 16 A FF + t 0 0 0 1 1 0 0 dataout2
19 14 A FF + t 0 0 0 1 1 0 0 dataout3
18 13 A FF + t 0 0 0 1 1 0 0 dataout4
6 3 A FF + t 0 0 0 1 1 0 0 dataout5
26 30 B FF + t 0 0 0 1 1 0 0 dataout6
20 15 A FF + t 0 0 0 1 2 0 0 dataout7
25 31 B FF + t 0 0 0 1 2 0 0 dataout8
24 32 B FF + t 0 0 0 1 2 0 0 dataout9
28 28 B FF + t 0 0 0 1 2 0 0 dataout10
37 21 B FF + t 0 0 0 1 2 0 0 dataout11
40 18 B FF + t 0 0 0 1 2 0 0 dataout12
36 22 B FF + t 0 0 0 1 2 0 0 dataout13
39 19 B FF + t 0 0 0 1 2 0 0 dataout14
16 11 A OUTPUT t 0 0 0 0 0 0 0 dataout15
41 17 B FF + t 0 0 0 7 10 1 0 p
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(4) 1 A TFFE + t 0 0 0 0 0 17 8 datahorl_flag (:42)
(34) 23 B DFFE + t 0 0 0 1 2 2 1 outhelp15 (:145)
(33) 24 B DFFE + t 0 0 0 1 2 2 1 outhelp14 (:146)
(32) 25 B DFFE + t 0 0 0 1 2 2 1 outhelp13 (:147)
(27) 29 B DFFE + t 0 0 0 1 2 2 1 outhelp12 (:148)
(38) 20 B DFFE + t 0 0 0 1 2 2 1 outhelp11 (:149)
(31) 26 B DFFE + t 0 0 0 1 2 2 1 outhelp10 (:150)
(29) 27 B DFFE + t 0 0 0 1 2 2 1 outhelp9 (:151)
(5) 2 A DFFE + t 0 0 0 1 2 2 1 outhelp8 (:152)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------------- LC12 con_count
| +------------------- LC6 dataout0
| | +----------------- LC5 dataout1
| | | +--------------- LC16 dataout2
| | | | +------------- LC14 dataout3
| | | | | +----------- LC13 dataout4
| | | | | | +--------- LC3 dataout5
| | | | | | | +------- LC15 dataout7
| | | | | | | | +----- LC11 dataout15
| | | | | | | | | +--- LC1 datahorl_flag
| | | | | | | | | | +- LC2 outhelp8
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> * * * * * * * * - * * | * * | <-- datahorl_flag
LC2 -> - - - - - - - * - - * | * * | <-- outhelp8
Pin
14 -> - - - - - - - * - - * | * - | <-- datain0
4 -> - * - - - - - - - - - | * * | <-- datain1
5 -> - - * - - - - - - - - | * * | <-- datain2
34 -> - - - * - - - - - - - | * * | <-- datain3
33 -> - - - - * - - - - - - | * * | <-- datain4
31 -> - - - - - * - - - - - | * * | <-- datain5
11 -> - - - - - - * - - - - | * * | <-- datain6
43 -> - - - - - - - - - - - | - - | <-- trans
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_quan.rpt
div_quan
** LOGIC CELL INTERCONNECTIONS **
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