📄 div_36k.rpt
字号:
- 1 - B 03 DFFE + 0 3 0 4 count_36k0 (:48)
- 4 - B 03 DFFE + 0 1 1 0 :50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_36k.rpt
div_36k
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_36k.rpt
div_36k
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_36k.rpt
div_36k
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC4_B3;
-- Node name is ':48' = 'count_36k0'
-- Equation name is 'count_36k0', location is LC1_B3, type is buried.
count_36k0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count_36k0
# !count_36k5 & !_LC1_B11 & !_LC4_B11;
-- Node name is ':47' = 'count_36k1'
-- Equation name is 'count_36k1', location is LC3_B3, type is buried.
count_36k1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count_36k0 & !count_36k1 & !_LC7_B3
# !count_36k0 & count_36k1 & !_LC7_B3;
-- Node name is ':46' = 'count_36k2'
-- Equation name is 'count_36k2', location is LC8_B3, type is buried.
count_36k2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !count_36k0 & count_36k2
# !count_36k1 & count_36k2
# count_36k2 & _LC7_B3
# count_36k0 & count_36k1 & !count_36k2 & !_LC7_B3;
-- Node name is ':45' = 'count_36k3'
-- Equation name is 'count_36k3', location is LC5_B11, type is buried.
count_36k3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = count_36k3 & !_LC6_B3 & !_LC7_B3
# !count_36k3 & _LC6_B3
# _LC6_B3 & _LC7_B3;
-- Node name is ':44' = 'count_36k4'
-- Equation name is 'count_36k4', location is LC3_B11, type is buried.
count_36k4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !count_36k3 & count_36k4
# count_36k4 & !_LC6_B3
# count_36k3 & !count_36k4 & _LC6_B3;
-- Node name is ':43' = 'count_36k5'
-- Equation name is 'count_36k5', location is LC2_B11, type is buried.
count_36k5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !count_36k3 & count_36k5
# count_36k5 & !_LC6_B3
# !count_36k4 & count_36k5
# count_36k3 & count_36k4 & !count_36k5 & _LC6_B3;
-- Node name is ':42' = 'count_36k6'
-- Equation name is 'count_36k6', location is LC8_B11, type is buried.
count_36k6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = count_36k6 & !_LC6_B11
# !count_36k6 & _LC6_B11;
-- Node name is ':41' = 'count_36k7'
-- Equation name is 'count_36k7', location is LC7_B11, type is buried.
count_36k7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = count_36k6 & !count_36k7 & _LC6_B11
# count_36k6 & _LC6_B11 & _LC7_B3
# !count_36k6 & count_36k7 & !_LC7_B3
# count_36k7 & !_LC6_B11 & !_LC7_B3;
-- Node name is '|lpm_add_sub:52|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ009);
_EQ009 = count_36k0 & count_36k1 & count_36k2 & !_LC7_B3;
-- Node name is '|lpm_add_sub:52|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ010);
_EQ010 = count_36k3 & count_36k4 & count_36k5 & _LC6_B3;
-- Node name is '~4~1'
-- Equation name is '~4~1', location is LC4_B11, type is buried.
-- synthesized logic cell
!_LC4_B11 = _LC4_B11~NOT;
_LC4_B11~NOT = LCELL( _EQ011);
_EQ011 = !count_36k2 & count_36k3 & !count_36k4;
-- Node name is '~4~2'
-- Equation name is '~4~2', location is LC1_B11, type is buried.
-- synthesized logic cell
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ012);
_EQ012 = count_36k1 & !count_36k6 & count_36k7;
-- Node name is ':4'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ013);
_EQ013 = count_36k0 & !count_36k5 & !_LC1_B11 & !_LC4_B11;
-- Node name is ':50'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE(!_LC4_B3, GLOBAL( clk), VCC, VCC, _LC7_B3);
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\div_36k.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,154K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -