div_quan.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 34 行

module div_quan(datain,trans,con_count,dataout,p);
input trans;
input[7:0] datain;
output con_count;
output p;
output[15:0] dataout;
reg p;
reg con_count;
reg[15:0] dataout;
reg[15:0] outhelp;
reg datahorl_flag;
reg[15:0] biaozhun;
always@(posedge trans)
begin
    biaozhun=5000;
	if(!datahorl_flag)
	begin
		outhelp[15:8]=datain;
		con_count=1;
	end
	if(datahorl_flag)
	begin
		outhelp[7:0]=datain;
		dataout=outhelp>>1;
		if(dataout==biaozhun)
        p=1;
		con_count=0;
	end
	datahorl_flag=1;
	if(!con_count)
		datahorl_flag=0;
    end
endmodule