fredivt.rpt

本代码为一个相位控制器的源程序

         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       3/ 96(  3%)    14/ 48( 29%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fredivt.rpt
fredivt

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       17         clk


Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fredivt.rpt
fredivt

** EQUATIONS **

clk      : INPUT;

-- Node name is 'clkout' 
-- Equation name is 'clkout', type is output 
clkout   =  _LC4_B4;

-- Node name is ':89' = 'count0' 
-- Equation name is 'count0', location is LC1_B4, type is buried.
count0   = DFFE(!count0,  clk,  VCC,  VCC,  VCC);

-- Node name is ':88' = 'count1' 
-- Equation name is 'count1', location is LC5_B4, type is buried.
count1   = DFFE( _EQ001,  clk,  VCC,  VCC,  VCC);
  _EQ001 =  count0 & !count1 & !_LC8_B12
         # !count0 &  count1 & !_LC8_B12;

-- Node name is ':87' = 'count2' 
-- Equation name is 'count2', location is LC1_B12, type is buried.
count2   = DFFE( _EQ002,  clk,  VCC,  VCC,  VCC);
  _EQ002 = !count0 &  count2 & !_LC8_B12
         # !count1 &  count2 & !_LC8_B12
         #  count0 &  count1 & !count2 & !_LC8_B12;

-- Node name is ':86' = 'count3' 
-- Equation name is 'count3', location is LC6_B9, type is buried.
count3   = DFFE( _EQ003,  clk,  VCC,  VCC,  VCC);
  _EQ003 =  count3 & !_LC6_B4 & !_LC8_B12
         # !count3 &  _LC6_B4 & !_LC8_B12;

-- Node name is ':85' = 'count4' 
-- Equation name is 'count4', location is LC5_B9, type is buried.
count4   = DFFE( _EQ004,  clk,  VCC,  VCC,  VCC);
  _EQ004 = !count3 &  count4
         #  count4 & !_LC6_B4
         #  count3 & !count4 &  _LC6_B4;

-- Node name is ':84' = 'count5' 
-- Equation name is 'count5', location is LC3_B3, type is buried.
count5   = DFFE( _EQ005,  clk,  VCC,  VCC,  VCC);
  _EQ005 =  count5 & !_LC2_B9 & !_LC8_B12
         # !count5 &  _LC2_B9 & !_LC8_B12;

-- Node name is ':83' = 'count6' 
-- Equation name is 'count6', location is LC1_B3, type is buried.
count6   = DFFE( _EQ006,  clk,  VCC,  VCC,  VCC);
  _EQ006 = !count5 &  count6 & !_LC8_B12
         #  count6 & !_LC2_B9 & !_LC8_B12
         #  count5 & !count6 &  _LC2_B9 & !_LC8_B12;

-- Node name is ':82' = 'count7' 
-- Equation name is 'count7', location is LC4_B9, type is buried.
count7   = DFFE( _EQ007,  clk,  VCC,  VCC,  VCC);
  _EQ007 =  count7 & !_LC4_B3 & !_LC8_B12
         # !count7 &  _LC4_B3 & !_LC8_B12;

-- Node name is ':81' = 'count8' 
-- Equation name is 'count8', location is LC7_B9, type is buried.
count8   = DFFE( _EQ008,  clk,  VCC,  VCC,  VCC);
  _EQ008 = !count7 &  count8 & !_LC8_B12
         #  count8 & !_LC4_B3 & !_LC8_B12
         #  count7 & !count8 &  _LC4_B3 & !_LC8_B12;

-- Node name is ':80' = 'count9' 
-- Equation name is 'count9', location is LC8_B3, type is buried.
count9   = DFFE( _EQ009,  clk,  VCC,  VCC,  VCC);
  _EQ009 =  count9 & !_LC8_B9 & !_LC8_B12
         # !count9 &  _LC8_B9 & !_LC8_B12;

-- Node name is ':79' = 'count10' 
-- Equation name is 'count10', location is LC6_B3, type is buried.
count10  = DFFE( _EQ010,  clk,  VCC,  VCC,  VCC);
  _EQ010 = !count9 &  count10
         #  count10 & !_LC8_B9
         #  count9 & !count10 &  _LC8_B9;

-- Node name is ':78' = 'count11' 
-- Equation name is 'count11', location is LC7_B3, type is buried.
count11  = DFFE( _EQ011,  clk,  VCC,  VCC,  VCC);
  _EQ011 = !count9 &  count11
         #  count11 & !_LC8_B9
         # !count10 &  count11
         #  count9 &  count10 & !count11 &  _LC8_B9;

-- Node name is ':77' = 'count12' 
-- Equation name is 'count12', location is LC7_B12, type is buried.
count12  = DFFE( _EQ012,  clk,  VCC,  VCC,  VCC);
  _EQ012 =  count12 & !_LC5_B3
         # !count12 &  _LC5_B3;

-- Node name is ':76' = 'count13' 
-- Equation name is 'count13', location is LC6_B12, type is buried.
count13  = DFFE( _EQ013,  clk,  VCC,  VCC,  VCC);
  _EQ013 = !count12 &  count13
         #  count13 & !_LC5_B3
         #  count12 & !count13 &  _LC5_B3;

-- Node name is ':75' = 'count14' 
-- Equation name is 'count14', location is LC5_B12, type is buried.
count14  = DFFE( _EQ014,  clk,  VCC,  VCC,  VCC);
  _EQ014 = !count13 &  count14
         # !count12 &  count14
         #  count14 & !_LC5_B3
         #  count12 &  count13 & !count14 &  _LC5_B3;

-- Node name is ':74' = 'count15' 
-- Equation name is 'count15', location is LC4_B12, type is buried.
count15  = DFFE( _EQ015,  clk,  VCC,  VCC,  VCC);
  _EQ015 = !count14 &  count15
         # !count13 &  count15
         #  count15 & !_LC3_B12
         #  count13 &  count14 & !count15 &  _LC3_B12;

-- Node name is '|lpm_add_sub:109|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ016);
  _EQ016 =  count0 &  count1 &  count2;

-- Node name is '|lpm_add_sub:109|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ017);
  _EQ017 =  count3 &  count4 &  _LC6_B4;

-- Node name is '|lpm_add_sub:109|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B3', type is buried 
_LC4_B3  = LCELL( _EQ018);
  _EQ018 =  count5 &  count6 &  _LC2_B9;

-- Node name is '|lpm_add_sub:109|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = LCELL( _EQ019);
  _EQ019 =  count7 &  count8 &  _LC4_B3;

-- Node name is '|lpm_add_sub:109|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ020);
  _EQ020 =  count9 &  count10 &  count11 &  _LC8_B9;

-- Node name is '|lpm_add_sub:109|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B12', type is buried 
_LC3_B12 = LCELL( _EQ021);
  _EQ021 =  count12 &  _LC5_B3;

-- Node name is '~4~1' 
-- Equation name is '~4~1', location is LC1_B9, type is buried.
-- synthesized logic cell 
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ022);
  _EQ022 = !count4 &  count5 &  count6 &  count7;

-- Node name is '~4~2' 
-- Equation name is '~4~2', location is LC2_B3, type is buried.
-- synthesized logic cell 
!_LC2_B3 = _LC2_B3~NOT;
_LC2_B3~NOT = LCELL( _EQ023);
  _EQ023 =  count9 & !count10 & !count11;

-- Node name is '~4~3' 
-- Equation name is '~4~3', location is LC3_B9, type is buried.
-- synthesized logic cell 
!_LC3_B9 = _LC3_B9~NOT;
_LC3_B9~NOT = LCELL( _EQ024);
  _EQ024 = !count3 &  count8 & !_LC1_B9 & !_LC2_B3;

-- Node name is '~4~4' 
-- Equation name is '~4~4', location is LC2_B12, type is buried.
-- synthesized logic cell 
!_LC2_B12 = _LC2_B12~NOT;
_LC2_B12~NOT = LCELL( _EQ025);
  _EQ025 = !count13 & !count14 & !count15;

-- Node name is ':4' 
-- Equation name is '_LC8_B12', type is buried 
_LC8_B12 = LCELL( _EQ026);
  _EQ026 = !count12 & !_LC2_B12 & !_LC3_B9 &  _LC6_B4;

-- Node name is ':107' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = DFFE(!_LC4_B4,  clk,  VCC,  VCC,  _LC8_B12);



Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fredivt.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,832K