fre_div.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 42 行

module fre_div(data16in,fre,freout,conf_in);
input[15:0] data16in;
input conf_in;
input fre;
output freout;
reg freout;
//reg ifcount_flag;
reg[15:0] datareg;
reg[15:0] count;
always@(data16in)
begin
	datareg=data16in;
	//if(datareg)
	//ifcount_flag=1;
	//if(!data16in)
	//begin
		//ifcount_flag2=0;
		//count=0;
	//end
end

always@(posedge fre)
 begin
 	if(count>datareg)
   	begin 
    	freout=~freout;
    	count=0;
   	end
	//if(count>datareg)
	//	count=datareg-1;
	//if(!conf_in)
 		count=count+1; 
	if(conf_in)
		begin
		count=0;
		freout=1;
		end
	//if(!ifcount_flag)
		//count=0;
 end
endmodule