📄 fre_test.rpt
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15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test.rpt
fre_test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 clk
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test.rpt
fre_test
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC2_B1;
-- Node name is ':89' = 'count0'
-- Equation name is 'count0', location is LC6_B7, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':88' = 'count1'
-- Equation name is 'count1', location is LC5_B7, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !count1 & !_LC1_B10
# !count0 & count1 & !_LC1_B10;
-- Node name is ':87' = 'count2'
-- Equation name is 'count2', location is LC7_B7, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count0 & count2 & !_LC1_B10
# !count1 & count2 & !_LC1_B10
# count0 & count1 & !count2 & !_LC1_B10;
-- Node name is ':86' = 'count3'
-- Equation name is 'count3', location is LC2_B7, type is buried.
count3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = count3 & !_LC1_B10 & !_LC3_B7
# !count3 & !_LC1_B10 & _LC3_B7;
-- Node name is ':85' = 'count4'
-- Equation name is 'count4', location is LC1_B7, type is buried.
count4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !count3 & count4
# count4 & !_LC3_B7
# count3 & !count4 & _LC3_B7;
-- Node name is ':84' = 'count5'
-- Equation name is 'count5', location is LC7_B11, type is buried.
count5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = count5 & !_LC1_B10 & !_LC4_B7
# !count5 & !_LC1_B10 & _LC4_B7;
-- Node name is ':83' = 'count6'
-- Equation name is 'count6', location is LC6_B11, type is buried.
count6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !count5 & count6 & !_LC1_B10
# count6 & !_LC1_B10 & !_LC4_B7
# count5 & !count6 & !_LC1_B10 & _LC4_B7;
-- Node name is ':82' = 'count7'
-- Equation name is 'count7', location is LC5_B11, type is buried.
count7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = count7 & !_LC1_B10 & !_LC4_B11
# !count7 & !_LC1_B10 & _LC4_B11;
-- Node name is ':81' = 'count8'
-- Equation name is 'count8', location is LC8_B11, type is buried.
count8 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !count7 & count8 & !_LC1_B10
# count8 & !_LC1_B10 & !_LC4_B11
# count7 & !count8 & !_LC1_B10 & _LC4_B11;
-- Node name is ':80' = 'count9'
-- Equation name is 'count9', location is LC5_B8, type is buried.
count9 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = count9 & !_LC1_B10 & !_LC1_B11
# !count9 & !_LC1_B10 & _LC1_B11;
-- Node name is ':79' = 'count10'
-- Equation name is 'count10', location is LC3_B8, type is buried.
count10 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !count9 & count10
# count10 & !_LC1_B11
# count9 & !count10 & _LC1_B11;
-- Node name is ':78' = 'count11'
-- Equation name is 'count11', location is LC4_B8, type is buried.
count11 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !count9 & count11
# count11 & !_LC1_B11
# !count10 & count11
# count9 & count10 & !count11 & _LC1_B11;
-- Node name is ':77' = 'count12'
-- Equation name is 'count12', location is LC7_B10, type is buried.
count12 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = count12 & !_LC1_B8
# !count12 & _LC1_B8;
-- Node name is ':76' = 'count13'
-- Equation name is 'count13', location is LC6_B10, type is buried.
count13 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !count12 & count13
# count13 & !_LC1_B8
# count12 & !count13 & _LC1_B8;
-- Node name is ':75' = 'count14'
-- Equation name is 'count14', location is LC5_B10, type is buried.
count14 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !count13 & count14
# !count12 & count14
# count14 & !_LC1_B8
# count12 & count13 & !count14 & _LC1_B8;
-- Node name is ':74' = 'count15'
-- Equation name is 'count15', location is LC4_B10, type is buried.
count15 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !count14 & count15
# !count13 & count15
# count15 & !_LC3_B10
# count13 & count14 & !count15 & _LC3_B10;
-- Node name is '|lpm_add_sub:109|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ016);
_EQ016 = count0 & count1 & count2;
-- Node name is '|lpm_add_sub:109|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ017);
_EQ017 = count3 & count4 & _LC3_B7;
-- Node name is '|lpm_add_sub:109|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ018);
_EQ018 = count5 & count6 & _LC4_B7;
-- Node name is '|lpm_add_sub:109|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ019);
_EQ019 = count7 & count8 & _LC4_B11;
-- Node name is '|lpm_add_sub:109|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ020);
_EQ020 = count9 & count10 & count11 & _LC1_B11;
-- Node name is '|lpm_add_sub:109|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ021);
_EQ021 = count12 & _LC1_B8;
-- Node name is '~4~1'
-- Equation name is '~4~1', location is LC3_B11, type is buried.
-- synthesized logic cell
!_LC3_B11 = _LC3_B11~NOT;
_LC3_B11~NOT = LCELL( _EQ022);
_EQ022 = !count4 & count5 & count6 & count7;
-- Node name is '~4~2'
-- Equation name is '~4~2', location is LC2_B8, type is buried.
-- synthesized logic cell
!_LC2_B8 = _LC2_B8~NOT;
_LC2_B8~NOT = LCELL( _EQ023);
_EQ023 = count9 & !count10 & !count11;
-- Node name is '~4~3'
-- Equation name is '~4~3', location is LC2_B11, type is buried.
-- synthesized logic cell
!_LC2_B11 = _LC2_B11~NOT;
_LC2_B11~NOT = LCELL( _EQ024);
_EQ024 = !count3 & count8 & !_LC2_B8 & !_LC3_B11;
-- Node name is '~4~4'
-- Equation name is '~4~4', location is LC2_B10, type is buried.
-- synthesized logic cell
!_LC2_B10 = _LC2_B10~NOT;
_LC2_B10~NOT = LCELL( _EQ025);
_EQ025 = !count13 & !count14 & !count15;
-- Node name is ':4'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ026);
_EQ026 = !count12 & !_LC2_B10 & !_LC2_B11 & _LC3_B7;
-- Node name is ':107'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE(!_LC2_B1, GLOBAL( clk), VCC, VCC, _LC1_B10);
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,414K
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