📄 p0test.rpt
字号:
112 - - - 03 OUTPUT 0 1 0 0 dataout3
111 - - - 02 OUTPUT 0 1 0 0 dataout4
110 - - - 01 OUTPUT 0 1 0 0 dataout5
109 - - - 01 OUTPUT 0 1 0 0 dataout6
102 - - A -- OUTPUT 0 1 0 0 dataout7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\p0test.rpt
p0test
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 06 LCELL s 1 0 1 0 dataout0~1
- 2 - A 03 LCELL s 1 0 1 0 dataout1~1
- 2 - A 04 LCELL s 1 0 1 0 dataout2~1
- 2 - C 03 LCELL s 1 0 1 0 dataout3~1
- 4 - A 01 LCELL s 1 0 1 0 dataout4~1
- 2 - B 02 LCELL s 1 0 1 0 dataout5~1
- 2 - B 01 LCELL s 1 0 1 0 dataout6~1
- 1 - B 12 LCELL s 1 0 1 0 dataout7~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\p0test.rpt
p0test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 1/ 48( 2%) 0/ 48( 0%) 5/16( 31%) 1/16( 6%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\p0test.rpt
p0test
** EQUATIONS **
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
datain4 : INPUT;
datain5 : INPUT;
datain6 : INPUT;
datain7 : INPUT;
-- Node name is 'dataout0~1'
-- Equation name is 'dataout0~1', location is LC4_A6, type is buried.
-- synthesized logic cell
_LC4_A6 = LCELL( datain0);
-- Node name is 'dataout0'
-- Equation name is 'dataout0', type is output
dataout0 = _LC4_A6;
-- Node name is 'dataout1~1'
-- Equation name is 'dataout1~1', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( datain1);
-- Node name is 'dataout1'
-- Equation name is 'dataout1', type is output
dataout1 = _LC2_A3;
-- Node name is 'dataout2~1'
-- Equation name is 'dataout2~1', location is LC2_A4, type is buried.
-- synthesized logic cell
_LC2_A4 = LCELL( datain2);
-- Node name is 'dataout2'
-- Equation name is 'dataout2', type is output
dataout2 = _LC2_A4;
-- Node name is 'dataout3~1'
-- Equation name is 'dataout3~1', location is LC2_C3, type is buried.
-- synthesized logic cell
_LC2_C3 = LCELL( datain3);
-- Node name is 'dataout3'
-- Equation name is 'dataout3', type is output
dataout3 = _LC2_C3;
-- Node name is 'dataout4~1'
-- Equation name is 'dataout4~1', location is LC4_A1, type is buried.
-- synthesized logic cell
_LC4_A1 = LCELL( datain4);
-- Node name is 'dataout4'
-- Equation name is 'dataout4', type is output
dataout4 = _LC4_A1;
-- Node name is 'dataout5~1'
-- Equation name is 'dataout5~1', location is LC2_B2, type is buried.
-- synthesized logic cell
_LC2_B2 = LCELL( datain5);
-- Node name is 'dataout5'
-- Equation name is 'dataout5', type is output
dataout5 = _LC2_B2;
-- Node name is 'dataout6~1'
-- Equation name is 'dataout6~1', location is LC2_B1, type is buried.
-- synthesized logic cell
_LC2_B1 = LCELL( datain6);
-- Node name is 'dataout6'
-- Equation name is 'dataout6', type is output
dataout6 = _LC2_B1;
-- Node name is 'dataout7~1'
-- Equation name is 'dataout7~1', location is LC1_B12, type is buried.
-- synthesized logic cell
_LC1_B12 = LCELL( datain7);
-- Node name is 'dataout7'
-- Equation name is 'dataout7', type is output
dataout7 = _LC1_B12;
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\p0test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,501K
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