📄 woxiang.rpt
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Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\woxiang.rpt
woxiang
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 clk
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\woxiang.rpt
woxiang
** EQUATIONS **
clk : INPUT;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC2_B1;
-- Node name is '|fredivt:1|:89' = '|fredivt:1|count0'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE(!_LC6_B7, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|fredivt:1|:88' = '|fredivt:1|count1'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_B10 & !_LC5_B7 & _LC6_B7
# !_LC1_B10 & _LC5_B7 & !_LC6_B7;
-- Node name is '|fredivt:1|:87' = '|fredivt:1|count2'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC1_B10 & !_LC6_B7 & _LC7_B7
# !_LC1_B10 & !_LC5_B7 & _LC7_B7
# !_LC1_B10 & _LC5_B7 & _LC6_B7 & !_LC7_B7;
-- Node name is '|fredivt:1|:86' = '|fredivt:1|count3'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_B10 & _LC2_B7 & !_LC3_B7
# !_LC1_B10 & !_LC2_B7 & _LC3_B7;
-- Node name is '|fredivt:1|:85' = '|fredivt:1|count4'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_B7 & !_LC2_B7
# _LC1_B7 & !_LC3_B7
# !_LC1_B7 & _LC2_B7 & _LC3_B7;
-- Node name is '|fredivt:1|:84' = '|fredivt:1|count5'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC1_B10 & !_LC4_B7 & _LC7_B11
# !_LC1_B10 & _LC4_B7 & !_LC7_B11;
-- Node name is '|fredivt:1|:83' = '|fredivt:1|count6'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC1_B10 & _LC6_B11 & !_LC7_B11
# !_LC1_B10 & !_LC4_B7 & _LC6_B11
# !_LC1_B10 & _LC4_B7 & !_LC6_B11 & _LC7_B11;
-- Node name is '|fredivt:1|:82' = '|fredivt:1|count7'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC1_B10 & !_LC4_B11 & _LC5_B11
# !_LC1_B10 & _LC4_B11 & !_LC5_B11;
-- Node name is '|fredivt:1|:81' = '|fredivt:1|count8'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC1_B10 & !_LC5_B11 & _LC8_B11
# !_LC1_B10 & !_LC4_B11 & _LC8_B11
# !_LC1_B10 & _LC4_B11 & _LC5_B11 & !_LC8_B11;
-- Node name is '|fredivt:1|:80' = '|fredivt:1|count9'
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC1_B10 & !_LC1_B11 & _LC5_B8
# !_LC1_B10 & _LC1_B11 & !_LC5_B8;
-- Node name is '|fredivt:1|:79' = '|fredivt:1|count10'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC3_B8 & !_LC5_B8
# !_LC1_B11 & _LC3_B8
# _LC1_B11 & !_LC3_B8 & _LC5_B8;
-- Node name is '|fredivt:1|:78' = '|fredivt:1|count11'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC4_B8 & !_LC5_B8
# !_LC1_B11 & _LC4_B8
# !_LC3_B8 & _LC4_B8
# _LC1_B11 & _LC3_B8 & !_LC4_B8 & _LC5_B8;
-- Node name is '|fredivt:1|:77' = '|fredivt:1|count12'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !_LC1_B8 & _LC7_B10
# _LC1_B8 & !_LC7_B10;
-- Node name is '|fredivt:1|:76' = '|fredivt:1|count13'
-- Equation name is '_LC6_B10', type is buried
_LC6_B10 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC6_B10 & !_LC7_B10
# !_LC1_B8 & _LC6_B10
# _LC1_B8 & !_LC6_B10 & _LC7_B10;
-- Node name is '|fredivt:1|:75' = '|fredivt:1|count14'
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC5_B10 & !_LC6_B10
# _LC5_B10 & !_LC7_B10
# !_LC1_B8 & _LC5_B10
# _LC1_B8 & !_LC5_B10 & _LC6_B10 & _LC7_B10;
-- Node name is '|fredivt:1|:74' = '|fredivt:1|count15'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC4_B10 & !_LC5_B10
# _LC4_B10 & !_LC6_B10
# !_LC3_B10 & _LC4_B10
# _LC3_B10 & !_LC4_B10 & _LC5_B10 & _LC6_B10;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ016);
_EQ016 = _LC5_B7 & _LC6_B7 & _LC7_B7;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ017);
_EQ017 = _LC1_B7 & _LC2_B7 & _LC3_B7;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ018);
_EQ018 = _LC4_B7 & _LC6_B11 & _LC7_B11;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ019);
_EQ019 = _LC4_B11 & _LC5_B11 & _LC8_B11;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ020);
_EQ020 = _LC1_B11 & _LC3_B8 & _LC4_B8 & _LC5_B8;
-- Node name is '|fredivt:1|lpm_add_sub:109|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ021);
_EQ021 = _LC1_B8 & _LC7_B10;
-- Node name is '|fredivt:1|~4~1'
-- Equation name is '_LC3_B11', type is buried
-- synthesized logic cell
!_LC3_B11 = _LC3_B11~NOT;
_LC3_B11~NOT = LCELL( _EQ022);
_EQ022 = !_LC1_B7 & _LC5_B11 & _LC6_B11 & _LC7_B11;
-- Node name is '|fredivt:1|~4~2'
-- Equation name is '_LC2_B8', type is buried
-- synthesized logic cell
!_LC2_B8 = _LC2_B8~NOT;
_LC2_B8~NOT = LCELL( _EQ023);
_EQ023 = !_LC3_B8 & !_LC4_B8 & _LC5_B8;
-- Node name is '|fredivt:1|~4~3'
-- Equation name is '_LC2_B11', type is buried
-- synthesized logic cell
!_LC2_B11 = _LC2_B11~NOT;
_LC2_B11~NOT = LCELL( _EQ024);
_EQ024 = !_LC2_B7 & !_LC2_B8 & !_LC3_B11 & _LC8_B11;
-- Node name is '|fredivt:1|~4~4'
-- Equation name is '_LC2_B10', type is buried
-- synthesized logic cell
!_LC2_B10 = _LC2_B10~NOT;
_LC2_B10~NOT = LCELL( _EQ025);
_EQ025 = !_LC4_B10 & !_LC5_B10 & !_LC6_B10;
-- Node name is '|fredivt:1|:4'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ026);
_EQ026 = !_LC2_B10 & !_LC2_B11 & _LC3_B7 & !_LC7_B10;
-- Node name is '|fredivt:1|:107'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE(!_LC2_B1, GLOBAL( clk), VCC, VCC, _LC1_B10);
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\woxiang.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,068K
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