fredivt.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 17 行

module fredivt(clk,clkout);
input clk;
output clkout;
reg clkout;
reg[15:0] count;
always@(posedge clk)
begin
	count=count+1;
	if(count==1000)
	begin
		
		clkout=~clkout;
		count=0;
	end
	end
endmodule