📄 fre_div.rpt
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-- Node name is '|lpm_add_sub:225|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ018);
_EQ018 = count0 & count1 & count2 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ019);
_EQ019 = count3 & _LC4_B2 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ020);
_EQ020 = count3 & count4 & _LC4_B2 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ021);
_EQ021 = count5 & !_LC5_B6 & _LC8_B2;
-- Node name is '|lpm_add_sub:225|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ022);
_EQ022 = count5 & count6 & !_LC5_B6 & _LC8_B2;
-- Node name is '|lpm_add_sub:225|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ023);
_EQ023 = count7 & _LC2_B11 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ024);
_EQ024 = count7 & count8 & _LC2_B11 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ025);
_EQ025 = count9 & !_LC5_B6 & _LC8_B9;
-- Node name is '|lpm_add_sub:225|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ026);
_EQ026 = count9 & count10 & !_LC5_B6 & _LC8_B9;
-- Node name is '|lpm_add_sub:225|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B1', type is buried
_LC7_B1 = LCELL( _EQ027);
_EQ027 = count11 & _LC5_B1 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ028);
_EQ028 = count11 & count12 & _LC5_B1 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ029);
_EQ029 = count13 & _LC4_B1 & !_LC5_B6;
-- Node name is '|lpm_add_sub:225|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = LCELL( _EQ030);
_EQ030 = count13 & count14 & _LC4_B1 & !_LC5_B6;
-- Node name is ':41'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ031);
_EQ031 = count15 & _LC2_B6
# !data16in15 & _LC2_B6
# count15 & !data16in15;
-- Node name is ':46'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ032);
_EQ032 = count14 & _LC1_B6
# !data16in14 & _LC1_B6
# count14 & !data16in14;
-- Node name is ':51'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ033);
_EQ033 = count13 & _LC2_B1
# !data16in13 & _LC2_B1
# count13 & !data16in13;
-- Node name is ':56'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ034);
_EQ034 = count12 & _LC3_B1
# !data16in12 & _LC3_B1
# count12 & !data16in12;
-- Node name is ':61'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ035);
_EQ035 = count11 & _LC1_B1
# !data16in11 & _LC1_B1
# count11 & !data16in11;
-- Node name is ':66'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ036);
_EQ036 = count10 & _LC4_B9
# !data16in10 & _LC4_B9
# count10 & !data16in10;
-- Node name is ':71'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ037);
_EQ037 = count9 & _LC2_B9
# !data16in9 & _LC2_B9
# count9 & !data16in9;
-- Node name is ':76'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ038);
_EQ038 = count8 & _LC1_B9
# !data16in8 & _LC1_B9
# count8 & !data16in8;
-- Node name is ':81'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ039);
_EQ039 = count7 & _LC3_B11
# !data16in7 & _LC3_B11
# count7 & !data16in7;
-- Node name is ':86'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ040);
_EQ040 = count6 & _LC1_B11
# !data16in6 & _LC1_B11
# count6 & !data16in6;
-- Node name is ':91'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ041);
_EQ041 = count5 & _LC2_B2
# !data16in5 & _LC2_B2
# count5 & !data16in5;
-- Node name is ':96'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ042);
_EQ042 = count4 & _LC3_B2
# !data16in4 & _LC3_B2
# count4 & !data16in4;
-- Node name is ':101'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ043);
_EQ043 = count3 & _LC1_B2
# !data16in3 & _LC1_B2
# count3 & !data16in3;
-- Node name is ':106'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ044);
_EQ044 = count2 & _LC1_B4
# !data16in2 & _LC1_B4
# count2 & !data16in2;
-- Node name is ':111'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ045);
_EQ045 = count1 & !data16in1
# count0 & count1 & !data16in0
# count0 & !data16in0 & !data16in1;
-- Node name is ':224'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( _EQ046, GLOBAL( fre), VCC, VCC, VCC);
_EQ046 = !_LC4_B11 & _LC5_B6
# _LC4_B11 & !_LC5_B6
# conf_in;
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_div.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:11
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:15
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,265K
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