📄 fre_div.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_div.rpt
fre_div
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 04 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:103
- 4 - B 02 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:107
- 6 - B 02 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:111
- 8 - B 02 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:115
- 6 - B 11 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:119
- 2 - B 11 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:123
- 5 - B 09 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:127
- 8 - B 09 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:131
- 6 - B 04 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:135
- 5 - B 01 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:139
- 7 - B 01 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:143
- 4 - B 01 AND2 0 4 0 3 |lpm_add_sub:225|addcore:adder|:147
- 4 - B 06 AND2 0 3 0 1 |lpm_add_sub:225|addcore:adder|:151
- 7 - B 06 AND2 0 4 0 1 |lpm_add_sub:225|addcore:adder|:155
- 5 - B 06 OR2 1 2 0 31 :41
- 2 - B 06 OR2 1 2 0 1 :46
- 1 - B 06 OR2 1 2 0 1 :51
- 2 - B 01 OR2 1 2 0 1 :56
- 3 - B 01 OR2 1 2 0 1 :61
- 1 - B 01 OR2 1 2 0 1 :66
- 4 - B 09 OR2 1 2 0 1 :71
- 2 - B 09 OR2 1 2 0 1 :76
- 1 - B 09 OR2 1 2 0 1 :81
- 3 - B 11 OR2 1 2 0 1 :86
- 1 - B 11 OR2 1 2 0 1 :91
- 2 - B 02 OR2 1 2 0 1 :96
- 3 - B 02 OR2 1 2 0 1 :101
- 1 - B 02 OR2 1 2 0 1 :106
- 1 - B 04 OR2 2 2 0 1 :111
- 8 - B 06 DFFE + 1 2 0 1 count15 (:201)
- 6 - B 06 DFFE + 1 2 0 2 count14 (:202)
- 3 - B 06 DFFE + 1 2 0 3 count13 (:203)
- 8 - B 01 DFFE + 1 2 0 2 count12 (:204)
- 6 - B 01 DFFE + 1 2 0 3 count11 (:205)
- 7 - B 04 DFFE + 1 2 0 2 count10 (:206)
- 2 - B 04 DFFE + 1 2 0 3 count9 (:207)
- 6 - B 09 DFFE + 1 2 0 2 count8 (:208)
- 3 - B 09 DFFE + 1 2 0 3 count7 (:209)
- 7 - B 11 DFFE + 1 2 0 2 count6 (:210)
- 5 - B 11 DFFE + 1 2 0 3 count5 (:211)
- 7 - B 02 DFFE + 1 2 0 2 count4 (:212)
- 5 - B 02 DFFE + 1 2 0 3 count3 (:213)
- 8 - B 04 DFFE + 1 2 0 2 count2 (:214)
- 5 - B 04 DFFE + 1 2 0 3 count1 (:215)
- 3 - B 04 DFFE + 1 1 0 4 count0 (:216)
- 4 - B 11 DFFE + 1 1 1 0 :224
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_div.rpt
fre_div
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 12/ 96( 12%) 17/ 48( 35%) 0/ 48( 0%) 12/16( 75%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_div.rpt
fre_div
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 fre
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fre_div.rpt
fre_div
** EQUATIONS **
conf_in : INPUT;
data16in0 : INPUT;
data16in1 : INPUT;
data16in2 : INPUT;
data16in3 : INPUT;
data16in4 : INPUT;
data16in5 : INPUT;
data16in6 : INPUT;
data16in7 : INPUT;
data16in8 : INPUT;
data16in9 : INPUT;
data16in10 : INPUT;
data16in11 : INPUT;
data16in12 : INPUT;
data16in13 : INPUT;
data16in14 : INPUT;
data16in15 : INPUT;
fre : INPUT;
-- Node name is ':216' = 'count0'
-- Equation name is 'count0', location is LC3_B4, type is buried.
count0 = DFFE( _EQ001, GLOBAL( fre), VCC, VCC, VCC);
_EQ001 = !conf_in & !count0
# !conf_in & _LC5_B6;
-- Node name is ':215' = 'count1'
-- Equation name is 'count1', location is LC5_B4, type is buried.
count1 = DFFE( _EQ002, GLOBAL( fre), VCC, VCC, VCC);
_EQ002 = !conf_in & count0 & !count1 & !_LC5_B6
# !conf_in & !count0 & count1 & !_LC5_B6;
-- Node name is ':214' = 'count2'
-- Equation name is 'count2', location is LC8_B4, type is buried.
count2 = DFFE( _EQ003, GLOBAL( fre), VCC, VCC, VCC);
_EQ003 = !conf_in & count2 & !_LC4_B4 & !_LC5_B6
# !conf_in & !count2 & _LC4_B4
# !conf_in & _LC4_B4 & _LC5_B6;
-- Node name is ':213' = 'count3'
-- Equation name is 'count3', location is LC5_B2, type is buried.
count3 = DFFE( _EQ004, GLOBAL( fre), VCC, VCC, VCC);
_EQ004 = !conf_in & count3 & !_LC4_B2 & !_LC5_B6
# !conf_in & !count3 & _LC4_B2
# !conf_in & _LC4_B2 & _LC5_B6;
-- Node name is ':212' = 'count4'
-- Equation name is 'count4', location is LC7_B2, type is buried.
count4 = DFFE( _EQ005, GLOBAL( fre), VCC, VCC, VCC);
_EQ005 = !conf_in & !count4 & _LC6_B2
# !conf_in & _LC5_B6 & _LC6_B2
# !conf_in & count4 & !_LC5_B6 & !_LC6_B2;
-- Node name is ':211' = 'count5'
-- Equation name is 'count5', location is LC5_B11, type is buried.
count5 = DFFE( _EQ006, GLOBAL( fre), VCC, VCC, VCC);
_EQ006 = !conf_in & !count5 & _LC8_B2
# !conf_in & _LC5_B6 & _LC8_B2
# !conf_in & count5 & !_LC5_B6 & !_LC8_B2;
-- Node name is ':210' = 'count6'
-- Equation name is 'count6', location is LC7_B11, type is buried.
count6 = DFFE( _EQ007, GLOBAL( fre), VCC, VCC, VCC);
_EQ007 = !conf_in & !count6 & _LC6_B11
# !conf_in & _LC5_B6 & _LC6_B11
# !conf_in & count6 & !_LC5_B6 & !_LC6_B11;
-- Node name is ':209' = 'count7'
-- Equation name is 'count7', location is LC3_B9, type is buried.
count7 = DFFE( _EQ008, GLOBAL( fre), VCC, VCC, VCC);
_EQ008 = !conf_in & !count7 & _LC2_B11
# !conf_in & _LC2_B11 & _LC5_B6
# !conf_in & count7 & !_LC2_B11 & !_LC5_B6;
-- Node name is ':208' = 'count8'
-- Equation name is 'count8', location is LC6_B9, type is buried.
count8 = DFFE( _EQ009, GLOBAL( fre), VCC, VCC, VCC);
_EQ009 = !conf_in & !count8 & _LC5_B9
# !conf_in & _LC5_B6 & _LC5_B9
# !conf_in & count8 & !_LC5_B6 & !_LC5_B9;
-- Node name is ':207' = 'count9'
-- Equation name is 'count9', location is LC2_B4, type is buried.
count9 = DFFE( _EQ010, GLOBAL( fre), VCC, VCC, VCC);
_EQ010 = !conf_in & !count9 & _LC8_B9
# !conf_in & _LC5_B6 & _LC8_B9
# !conf_in & count9 & !_LC5_B6 & !_LC8_B9;
-- Node name is ':206' = 'count10'
-- Equation name is 'count10', location is LC7_B4, type is buried.
count10 = DFFE( _EQ011, GLOBAL( fre), VCC, VCC, VCC);
_EQ011 = !conf_in & !count10 & _LC6_B4
# !conf_in & _LC5_B6 & _LC6_B4
# !conf_in & count10 & !_LC5_B6 & !_LC6_B4;
-- Node name is ':205' = 'count11'
-- Equation name is 'count11', location is LC6_B1, type is buried.
count11 = DFFE( _EQ012, GLOBAL( fre), VCC, VCC, VCC);
_EQ012 = !conf_in & !count11 & _LC5_B1
# !conf_in & _LC5_B1 & _LC5_B6
# !conf_in & count11 & !_LC5_B1 & !_LC5_B6;
-- Node name is ':204' = 'count12'
-- Equation name is 'count12', location is LC8_B1, type is buried.
count12 = DFFE( _EQ013, GLOBAL( fre), VCC, VCC, VCC);
_EQ013 = !conf_in & !count12 & _LC7_B1
# !conf_in & _LC5_B6 & _LC7_B1
# !conf_in & count12 & !_LC5_B6 & !_LC7_B1;
-- Node name is ':203' = 'count13'
-- Equation name is 'count13', location is LC3_B6, type is buried.
count13 = DFFE( _EQ014, GLOBAL( fre), VCC, VCC, VCC);
_EQ014 = !conf_in & !count13 & _LC4_B1
# !conf_in & _LC4_B1 & _LC5_B6
# !conf_in & count13 & !_LC4_B1 & !_LC5_B6;
-- Node name is ':202' = 'count14'
-- Equation name is 'count14', location is LC6_B6, type is buried.
count14 = DFFE( _EQ015, GLOBAL( fre), VCC, VCC, VCC);
_EQ015 = !conf_in & !count14 & _LC4_B6
# !conf_in & _LC4_B6 & _LC5_B6
# !conf_in & count14 & !_LC4_B6 & !_LC5_B6;
-- Node name is ':201' = 'count15'
-- Equation name is 'count15', location is LC8_B6, type is buried.
count15 = DFFE( _EQ016, GLOBAL( fre), VCC, VCC, VCC);
_EQ016 = !conf_in & !count15 & _LC7_B6
# !conf_in & _LC5_B6 & _LC7_B6
# !conf_in & count15 & !_LC5_B6 & !_LC7_B6;
-- Node name is 'freout'
-- Equation name is 'freout', type is output
freout = _LC4_B11;
-- Node name is '|lpm_add_sub:225|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ017);
_EQ017 = count0 & count1 & !_LC5_B6;
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