📄 fretest.rpt
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-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = DFFE( _EQ051, bin, VCC, VCC, VCC);
_EQ051 = !_LC2_A22 & _LC4_A24 & !_LC6_A17 & _LC8_A22
# _LC2_A22 & !_LC6_A17 & !_LC8_A22
# _LC2_A22 & !_LC4_A24 & !_LC6_A17;
-- Node name is '|fre_div:2|:204' = '|fre_div:2|count12'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = DFFE( _EQ052, bin, VCC, VCC, VCC);
_EQ052 = !_LC3_A22 & _LC6_A22
# _LC6_A17 & _LC6_A22
# _LC3_A22 & !_LC6_A17 & !_LC6_A22;
-- Node name is '|fre_div:2|:203' = '|fre_div:2|count13'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = DFFE( _EQ053, bin, VCC, VCC, VCC);
_EQ053 = _LC3_A22 & !_LC4_A22 & !_LC6_A17 & _LC6_A22
# !_LC3_A22 & _LC4_A22 & !_LC6_A17
# _LC4_A22 & !_LC6_A17 & !_LC6_A22;
-- Node name is '|fre_div:2|:202' = '|fre_div:2|count14'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = DFFE( _EQ054, bin, VCC, VCC, VCC);
_EQ054 = !_LC5_A22 & _LC7_A22
# _LC6_A17 & _LC7_A22
# _LC5_A22 & !_LC6_A17 & !_LC7_A22;
-- Node name is '|fre_div:2|:201' = '|fre_div:2|count15'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE( _EQ055, bin, VCC, VCC, VCC);
_EQ055 = !_LC1_A22 & _LC5_A22 & !_LC6_A17 & _LC7_A22
# _LC1_A22 & !_LC5_A22 & !_LC6_A17
# _LC1_A22 & !_LC6_A17 & !_LC7_A22;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ056);
_EQ056 = _LC1_A17 & _LC4_A13 & !_LC6_A17;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ057);
_EQ057 = _LC5_A13 & _LC6_A13 & !_LC6_A17 & _LC7_A13;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ058);
_EQ058 = _LC2_A24 & _LC5_A21 & !_LC6_A17 & _LC8_A13;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ059);
_EQ059 = _LC1_A24 & !_LC6_A17 & _LC7_A24 & _LC8_A24;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ060);
_EQ060 = _LC3_A24 & _LC5_A24 & !_LC6_A17 & _LC6_A24;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ061);
_EQ061 = _LC2_A22 & _LC4_A24 & !_LC6_A17 & _LC8_A22;
-- Node name is '|fre_div:2|lpm_add_sub:225|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ062);
_EQ062 = _LC3_A22 & _LC4_A22 & !_LC6_A17 & _LC6_A22;
-- Node name is '|fre_div:2|:41'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = LCELL( _EQ063);
_EQ063 = _LC1_A22 & _LC8_A17
# !data16in15 & _LC8_A17
# !data16in15 & _LC1_A22;
-- Node name is '|fre_div:2|:46'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = LCELL( _EQ064);
_EQ064 = _LC5_A22 & _LC7_A17
# !data16in14 & _LC7_A17
# !data16in14 & _LC5_A22;
-- Node name is '|fre_div:2|:51'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ065);
_EQ065 = _LC4_A22 & _LC5_A17
# !data16in13 & _LC5_A17
# !data16in13 & _LC4_A22;
-- Node name is '|fre_div:2|:56'
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = LCELL( _EQ066);
_EQ066 = _LC3_A22 & _LC4_A17
# !data16in12 & _LC4_A17
# !data16in12 & _LC3_A22;
-- Node name is '|fre_div:2|:61'
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = LCELL( _EQ067);
_EQ067 = _LC2_A17 & _LC2_A22
# !data16in11 & _LC2_A17
# !data16in11 & _LC2_A22;
-- Node name is '|fre_div:2|:66'
-- Equation name is '_LC2_A17', type is buried
_LC2_A17 = LCELL( _EQ068);
_EQ068 = _LC6_A21 & _LC8_A22
# !data16in10 & _LC6_A21
# !data16in10 & _LC8_A22;
-- Node name is '|fre_div:2|:71'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ069);
_EQ069 = _LC3_A24 & _LC8_A21
# !data16in9 & _LC8_A21
# !data16in9 & _LC3_A24;
-- Node name is '|fre_div:2|:76'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ070);
_EQ070 = _LC5_A24 & _LC7_A21
# !data16in8 & _LC7_A21
# !data16in8 & _LC5_A24;
-- Node name is '|fre_div:2|:81'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ071);
_EQ071 = _LC4_A21 & _LC8_A24
# !data16in7 & _LC4_A21
# !data16in7 & _LC8_A24;
-- Node name is '|fre_div:2|:86'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ072);
_EQ072 = _LC3_A21 & _LC7_A24
# !data16in6 & _LC3_A21
# !data16in6 & _LC7_A24;
-- Node name is '|fre_div:2|:91'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ073);
_EQ073 = _LC2_A21 & _LC2_A24
# !data16in5 & _LC2_A21
# !data16in5 & _LC2_A24;
-- Node name is '|fre_div:2|:96'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ074);
_EQ074 = _LC2_A13 & _LC5_A21
# !data16in4 & _LC2_A13
# !data16in4 & _LC5_A21;
-- Node name is '|fre_div:2|:101'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ075);
_EQ075 = _LC3_A13 & _LC7_A13
# !data16in3 & _LC3_A13
# !data16in3 & _LC7_A13;
-- Node name is '|fre_div:2|:106'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ076);
_EQ076 = _LC1_A13 & _LC6_A13
# !data16in2 & _LC1_A13
# !data16in2 & _LC6_A13;
-- Node name is '|fre_div:2|:111'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ077);
_EQ077 = !data16in1 & _LC4_A13
# !data16in0 & _LC1_A17 & _LC4_A13
# !data16in0 & !data16in1 & _LC1_A17;
-- Node name is '|fre_div:2|:224'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = DFFE( _EQ078, bin, VCC, VCC, VCC);
_EQ078 = data16in15 & !_LC1_A22 & _LC3_A17
# data16in15 & _LC3_A17 & !_LC8_A17
# !_LC1_A22 & _LC3_A17 & !_LC8_A17
# _LC1_A22 & !_LC3_A17 & _LC8_A17
# !data16in15 & !_LC3_A17 & _LC8_A17
# !data16in15 & _LC1_A22 & !_LC3_A17;
Project Informatione:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:18
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:22
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,033K
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