📄 fretest.rpt
字号:
46 - - - 17 INPUT 0 0 0 2 data16in12
47 - - - 16 INPUT 0 0 0 2 data16in13
48 - - - 15 INPUT 0 0 0 2 data16in14
49 - - - 14 INPUT 0 0 0 4 data16in15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
fretest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - C -- OUTPUT 0 1 0 0 aout
81 - - C -- OUTPUT 0 1 0 0 bout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
fretest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 14 AND2 0 3 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:103
- 7 - A 14 AND2 0 4 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:111
- 8 - A 15 AND2 0 4 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:119
- 8 - A 18 AND2 0 4 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:127
- 4 - A 18 AND2 0 4 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:135
- 2 - B 19 AND2 0 4 0 3 |fre_div:1|lpm_add_sub:225|addcore:adder|:143
- 5 - B 19 AND2 0 4 0 2 |fre_div:1|lpm_add_sub:225|addcore:adder|:151
- 2 - B 20 OR2 1 2 0 23 |fre_div:1|:41
- 8 - B 20 OR2 1 2 0 2 |fre_div:1|:46
- 7 - B 20 OR2 1 2 0 1 |fre_div:1|:51
- 6 - B 20 OR2 1 2 0 1 |fre_div:1|:56
- 5 - B 20 OR2 1 2 0 1 |fre_div:1|:61
- 3 - B 20 OR2 1 2 0 1 |fre_div:1|:66
- 1 - B 20 OR2 1 2 0 1 |fre_div:1|:71
- 1 - A 21 OR2 1 2 0 1 |fre_div:1|:76
- 1 - A 18 OR2 1 2 0 1 |fre_div:1|:81
- 3 - A 18 OR2 1 2 0 1 |fre_div:1|:86
- 1 - A 15 OR2 1 2 0 1 |fre_div:1|:91
- 3 - A 15 OR2 1 2 0 1 |fre_div:1|:96
- 2 - A 15 OR2 1 2 0 1 |fre_div:1|:101
- 4 - A 14 OR2 1 2 0 1 |fre_div:1|:106
- 1 - A 14 OR2 2 2 0 1 |fre_div:1|:111
- 8 - B 19 DFFE 1 3 0 2 |fre_div:1|count15 (|fre_div:1|:201)
- 6 - B 19 DFFE 1 2 0 2 |fre_div:1|count14 (|fre_div:1|:202)
- 7 - B 19 DFFE 1 3 0 2 |fre_div:1|count13 (|fre_div:1|:203)
- 3 - B 19 DFFE 1 2 0 3 |fre_div:1|count12 (|fre_div:1|:204)
- 4 - B 19 DFFE 1 3 0 2 |fre_div:1|count11 (|fre_div:1|:205)
- 1 - B 19 DFFE 1 2 0 3 |fre_div:1|count10 (|fre_div:1|:206)
- 2 - A 18 DFFE 1 3 0 2 |fre_div:1|count9 (|fre_div:1|:207)
- 6 - A 18 DFFE 1 2 0 3 |fre_div:1|count8 (|fre_div:1|:208)
- 7 - A 18 DFFE 1 3 0 2 |fre_div:1|count7 (|fre_div:1|:209)
- 5 - A 18 DFFE 1 2 0 3 |fre_div:1|count6 (|fre_div:1|:210)
- 5 - A 15 DFFE 1 3 0 2 |fre_div:1|count5 (|fre_div:1|:211)
- 4 - A 15 DFFE 1 2 0 3 |fre_div:1|count4 (|fre_div:1|:212)
- 6 - A 14 DFFE 1 3 0 2 |fre_div:1|count3 (|fre_div:1|:213)
- 8 - A 14 DFFE 1 2 0 3 |fre_div:1|count2 (|fre_div:1|:214)
- 3 - A 14 DFFE 1 2 0 2 |fre_div:1|count1 (|fre_div:1|:215)
- 2 - A 14 DFFE 1 1 0 3 |fre_div:1|count0 (|fre_div:1|:216)
- 4 - B 20 DFFE 2 2 1 0 |fre_div:1|:224
- 5 - A 13 AND2 0 3 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:103
- 8 - A 13 AND2 0 4 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:111
- 1 - A 24 AND2 0 4 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:119
- 6 - A 24 AND2 0 4 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:127
- 4 - A 24 AND2 0 4 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:135
- 6 - A 22 AND2 0 4 0 3 |fre_div:2|lpm_add_sub:225|addcore:adder|:143
- 7 - A 22 AND2 0 4 0 2 |fre_div:2|lpm_add_sub:225|addcore:adder|:151
- 6 - A 17 OR2 1 2 0 23 |fre_div:2|:41
- 8 - A 17 OR2 1 2 0 2 |fre_div:2|:46
- 7 - A 17 OR2 1 2 0 1 |fre_div:2|:51
- 5 - A 17 OR2 1 2 0 1 |fre_div:2|:56
- 4 - A 17 OR2 1 2 0 1 |fre_div:2|:61
- 2 - A 17 OR2 1 2 0 1 |fre_div:2|:66
- 6 - A 21 OR2 1 2 0 1 |fre_div:2|:71
- 8 - A 21 OR2 1 2 0 1 |fre_div:2|:76
- 7 - A 21 OR2 1 2 0 1 |fre_div:2|:81
- 4 - A 21 OR2 1 2 0 1 |fre_div:2|:86
- 3 - A 21 OR2 1 2 0 1 |fre_div:2|:91
- 2 - A 21 OR2 1 2 0 1 |fre_div:2|:96
- 2 - A 13 OR2 1 2 0 1 |fre_div:2|:101
- 3 - A 13 OR2 1 2 0 1 |fre_div:2|:106
- 1 - A 13 OR2 2 2 0 1 |fre_div:2|:111
- 1 - A 22 DFFE 1 3 0 2 |fre_div:2|count15 (|fre_div:2|:201)
- 5 - A 22 DFFE 1 2 0 2 |fre_div:2|count14 (|fre_div:2|:202)
- 4 - A 22 DFFE 1 3 0 2 |fre_div:2|count13 (|fre_div:2|:203)
- 3 - A 22 DFFE 1 2 0 3 |fre_div:2|count12 (|fre_div:2|:204)
- 2 - A 22 DFFE 1 3 0 2 |fre_div:2|count11 (|fre_div:2|:205)
- 8 - A 22 DFFE 1 2 0 3 |fre_div:2|count10 (|fre_div:2|:206)
- 3 - A 24 DFFE 1 3 0 2 |fre_div:2|count9 (|fre_div:2|:207)
- 5 - A 24 DFFE 1 2 0 3 |fre_div:2|count8 (|fre_div:2|:208)
- 8 - A 24 DFFE 1 3 0 2 |fre_div:2|count7 (|fre_div:2|:209)
- 7 - A 24 DFFE 1 2 0 3 |fre_div:2|count6 (|fre_div:2|:210)
- 2 - A 24 DFFE 1 3 0 2 |fre_div:2|count5 (|fre_div:2|:211)
- 5 - A 21 DFFE 1 2 0 3 |fre_div:2|count4 (|fre_div:2|:212)
- 7 - A 13 DFFE 1 3 0 2 |fre_div:2|count3 (|fre_div:2|:213)
- 6 - A 13 DFFE 1 2 0 3 |fre_div:2|count2 (|fre_div:2|:214)
- 4 - A 13 DFFE 1 2 0 2 |fre_div:2|count1 (|fre_div:2|:215)
- 1 - A 17 DFFE 1 1 0 3 |fre_div:2|count0 (|fre_div:2|:216)
- 3 - A 17 DFFE 2 2 1 0 |fre_div:2|:224
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
fretest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 12/ 96( 12%) 0/ 48( 0%) 33/ 48( 68%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 17/ 48( 35%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
fretest
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 ain
INPUT 17 bin
Device-Specific Information:e:\dragon'sfile\sourecode\phasemeasure\phaseverilog2\fretest.rpt
fretest
** EQUATIONS **
ain : INPUT;
bin : INPUT;
data16in0 : INPUT;
data16in1 : INPUT;
data16in2 : INPUT;
data16in3 : INPUT;
data16in4 : INPUT;
data16in5 : INPUT;
data16in6 : INPUT;
data16in7 : INPUT;
data16in8 : INPUT;
data16in9 : INPUT;
data16in10 : INPUT;
data16in11 : INPUT;
data16in12 : INPUT;
data16in13 : INPUT;
data16in14 : INPUT;
data16in15 : INPUT;
-- Node name is 'aout'
-- Equation name is 'aout', type is output
aout = _LC4_B20;
-- Node name is 'bout'
-- Equation name is 'bout', type is output
bout = _LC3_A17;
-- Node name is '|fre_div:1|:216' = '|fre_div:1|count0'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _EQ001, ain, VCC, VCC, VCC);
_EQ001 = !_LC2_A14
# _LC2_B20;
-- Node name is '|fre_div:1|:215' = '|fre_div:1|count1'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = DFFE( _EQ002, ain, VCC, VCC, VCC);
_EQ002 = _LC2_A14 & !_LC2_B20 & !_LC3_A14
# !_LC2_A14 & !_LC2_B20 & _LC3_A14;
-- Node name is '|fre_div:1|:214' = '|fre_div:1|count2'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = DFFE( _EQ003, ain, VCC, VCC, VCC);
_EQ003 = !_LC2_B20 & !_LC5_A14 & _LC8_A14
# _LC5_A14 & !_LC8_A14
# _LC2_B20 & _LC5_A14;
-- Node name is '|fre_div:1|:213' = '|fre_div:1|count3'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = DFFE( _EQ004, ain, VCC, VCC, VCC);
_EQ004 = !_LC2_B20 & _LC6_A14 & !_LC8_A14
# !_LC2_B20 & !_LC5_A14 & _LC6_A14
# !_LC2_B20 & _LC5_A14 & !_LC6_A14 & _LC8_A14;
-- Node name is '|fre_div:1|:212' = '|fre_div:1|count4'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = DFFE( _EQ005, ain, VCC, VCC, VCC);
_EQ005 = !_LC4_A15 & _LC7_A14
# _LC2_B20 & _LC7_A14
# !_LC2_B20 & _LC4_A15 & !_LC7_A14;
-- Node name is '|fre_div:1|:211' = '|fre_div:1|count5'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ006, ain, VCC, VCC, VCC);
_EQ006 = !_LC2_B20 & _LC4_A15 & !_LC5_A15 & _LC7_A14
# !_LC2_B20 & !_LC4_A15 & _LC5_A15
# !_LC2_B20 & _LC5_A15 & !_LC7_A14;
-- Node name is '|fre_div:1|:210' = '|fre_div:1|count6'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = DFFE( _EQ007, ain, VCC, VCC, VCC);
_EQ007 = !_LC5_A18 & _LC8_A15
# _LC2_B20 & _LC8_A15
# !_LC2_B20 & _LC5_A18 & !_LC8_A15;
-- Node name is '|fre_div:1|:209' = '|fre_div:1|count7'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = DFFE( _EQ008, ain, VCC, VCC, VCC);
_EQ008 = !_LC2_B20 & _LC5_A18 & !_LC7_A18 & _LC8_A15
# !_LC2_B20 & !_LC5_A18 & _LC7_A18
# !_LC2_B20 & _LC7_A18 & !_LC8_A15;
-- Node name is '|fre_div:1|:208' = '|fre_div:1|count8'
-- Equation name is '_LC6_A18', type is buried
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