fre_divcs.v

来自「本代码为一个相位控制器的源程序」· Verilog 代码 · 共 28 行

module fre_divcs(fre,freout);
//input[15:0] data16in;
input fre;
output freout;
reg freout;
reg ifcount_flag;
//reg[15:0] datareg;
reg[15:0] count;
/*always@(data16in)
begin
	//datareg=data16in;
	//ifcount_flag=1;
	///if(!data16in)
		ifcount_flag=0;
end*/

always@(posedge fre)
 begin
 	if(count==1000)
   	begin 
    	freout=~freout;
    	count=0;
   	end
	//if(ifcount_flag)
 		count=count+1; 
 end
endmodule