📄 shumaguan.rpt
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Device-Specific Information: d:\dragon\shumaguan.rpt
shumaguan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 06 DFFE + 0 2 1 8 :16
- 7 - C 06 DFFE + 0 1 1 9 :17
- 4 - A 08 DFFE + 0 0 1 10 :18
- 4 - C 06 DFFE + 0 3 1 0 :51
- 1 - C 06 DFFE + 0 3 1 0 :52
- 2 - C 06 DFFE + 0 3 1 0 :53
- 3 - C 06 DFFE + 0 3 1 0 :54
- 5 - C 06 DFFE + 0 3 1 0 :55
- 6 - C 06 DFFE + 0 3 1 0 :56
- 4 - B 01 DFFE + 0 3 1 0 :57
- 4 - B 03 DFFE + 0 3 1 0 :58
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\shumaguan.rpt
shumaguan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\shumaguan.rpt
shumaguan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: d:\dragon\shumaguan.rpt
shumaguan
** EQUATIONS **
clk : INPUT;
-- Node name is 'k0'
-- Equation name is 'k0', type is output
k0 = _LC4_A8;
-- Node name is 'k1'
-- Equation name is 'k1', type is output
k1 = _LC7_C6;
-- Node name is 'k2'
-- Equation name is 'k2', type is output
k2 = _LC8_C6;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC4_B3;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC4_B1;
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = _LC6_C6;
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = _LC5_C6;
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = _LC3_C6;
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = _LC2_C6;
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = _LC1_C6;
-- Node name is 'out7'
-- Equation name is 'out7', type is output
out7 = _LC4_C6;
-- Node name is ':16'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC7_C6 & _LC8_C6
# !_LC4_A8 & _LC8_C6
# _LC4_A8 & _LC7_C6 & !_LC8_C6;
-- Node name is ':17'
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC4_A8 & _LC7_C6
# _LC4_A8 & !_LC7_C6;
-- Node name is ':18'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = DFFE(!_LC4_A8, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':51'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC4_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':52'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':53'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC2_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':54'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC3_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':55'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC5_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':56'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC6_C6
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':57'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC4_B1
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
-- Node name is ':58'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC4_B3
# !_LC4_A8 & !_LC7_C6 & !_LC8_C6;
Project Information d:\dragon\shumaguan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,078K
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