jtdtest02.v

在maxplusII平台上开发的一个交通等内核

module jtdtest02(clk,out1,i);
input clk;
output[7:0] out1;
output[3:0] i;
reg[7:0] out1;
reg[2:0] i;
reg[3:0] second;
reg[2:0] minute;
reg[7:0] secondo;
reg[7:0] minuteo;
reg[10:0] k;
always@(posedge clk)
begin
case(second)
0:begin secondo=8'b00111111;end
9:begin secondo=8'b00000110;end
8:begin secondo=8'b01011011;end
7:begin secondo=8'b01001111;end
6:begin secondo=8'b01100110;end
5:begin secondo=8'b01101101;end
4:begin secondo=8'b01111101;end
3:begin secondo=8'b00000111;end
2:begin secondo=8'b01111111;end
1:begin secondo=8'b01101111;end
endcase
case(minute)
0:begin minuteo=8'b00111111;end
6:begin minuteo=8'b00000110;end
5:begin minuteo=8'b01011011;end
4:begin minuteo=8'b01001111;end
3:begin minuteo=8'b01100110;end
2:begin minuteo=8'b01101101;end
1:begin minuteo=8'b01111101;end
endcase
i=i+1;
k=k+1;
if(k<498)
  begin		   
				for(i=0;i<5;i=i+1)
				case (i)
				 1:begin out1=secondo;end
				 2:begin out1=minuteo;end
				 3:begin out1=secondo;end
				 4:begin out1=minuteo;end		
				endcase
				i=i+1;
		k=k+1;		             
  end
k=0;
second=second+1;
if(second==10)
	begin
		minute=minute+1;
			if(minute==6)
			minute=minute-6;
	    minute=minute-10;
	end
end
endmodule