📄 light.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\light.rpt
light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\light.rpt
light
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\dragon\light.rpt
light
** EQUATIONS **
clk : INPUT;
-- Node name is ':63' = 'i0'
-- Equation name is 'i0', location is LC5_C4, type is buried.
i0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !i0 & !_LC7_C3;
-- Node name is ':62' = 'i1'
-- Equation name is 'i1', location is LC4_C3, type is buried.
i1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = i0 & _LC2_C3
# _LC2_C3 & _LC7_C3;
-- Node name is ':61' = 'i2'
-- Equation name is 'i2', location is LC8_C3, type is buried.
i2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = i0 & _LC5_C3
# _LC5_C3 & _LC7_C3;
-- Node name is ':60' = 'i3'
-- Equation name is 'i3', location is LC2_C4, type is buried.
i3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = i0 & _LC1_C3
# _LC1_C3 & _LC7_C3;
-- Node name is ':59' = 'i4'
-- Equation name is 'i4', location is LC7_C4, type is buried.
i4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = i0 & _LC4_C4
# _LC4_C4 & _LC7_C3;
-- Node name is ':58' = 'i5'
-- Equation name is 'i5', location is LC3_C4, type is buried.
i5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = i0 & _LC6_C4
# _LC6_C4 & _LC7_C3;
-- Node name is ':57' = 'i6'
-- Equation name is 'i6', location is LC5_C2, type is buried.
i6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = i0 & _LC4_C2
# _LC4_C2 & _LC7_C3;
-- Node name is ':56' = 'i7'
-- Equation name is 'i7', location is LC2_C2, type is buried.
i7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = i0 & _LC6_C2
# _LC6_C2 & _LC7_C3;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC2_C6;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC6_C3;
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = _LC3_C3;
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = _LC8_C4;
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = _LC7_C2;
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = _LC3_C2;
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = _LC8_C2;
-- Node name is 'out7'
-- Equation name is 'out7', type is output
out7 = _LC1_C4;
-- Node name is '|lpm_mult:98|multcore:mult_core|romout0_1' from file "multcore.tdf" line 676, column 33
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( i0);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout0_2' from file "multcore.tdf" line 676, column 33
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = LCELL( i1);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout0_3' from file "multcore.tdf" line 676, column 33
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( i2);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout0_4' from file "multcore.tdf" line 676, column 33
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = LCELL( i3);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout1_1' from file "multcore.tdf" line 710, column 38
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( i4);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout1_2' from file "multcore.tdf" line 710, column 38
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( i5);
-- Node name is '|lpm_mult:98|multcore:mult_core|romout1_3' from file "multcore.tdf" line 710, column 38
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( i6);
-- Node name is '~21~1'
-- Equation name is '~21~1', location is LC1_C2, type is buried.
-- synthesized logic cell
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ009);
_EQ009 = !i4 & !i5 & !i6 & !i7;
-- Node name is '~21~2'
-- Equation name is '~21~2', location is LC7_C3, type is buried.
-- synthesized logic cell
!_LC7_C3 = _LC7_C3~NOT;
_LC7_C3~NOT = LCELL( _EQ010);
_EQ010 = !i1 & !i2 & !i3 & !_LC1_C2;
-- Node name is ':89'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !i0 & _LC1_C4 & !_LC7_C3
# i7;
-- Node name is ':90'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !i0 & !_LC7_C3 & _LC8_C2
# i6;
-- Node name is ':91'
-- Equation name is '_LC3_C2', type is buried
_LC3_C2 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !i0 & _LC3_C2 & !_LC7_C3
# i5;
-- Node name is ':92'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !i0 & _LC7_C2 & !_LC7_C3
# i4;
-- Node name is ':93'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !i0 & !_LC7_C3 & _LC8_C4
# i3;
-- Node name is ':94'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !i0 & _LC3_C3 & !_LC7_C3
# i2;
-- Node name is ':95'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = !i0 & _LC6_C3 & !_LC7_C3
# i1;
-- Node name is ':96'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC2_C6 & !_LC7_C3
# i0;
Project Information d:\dragon\light.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,352K
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