📄 jtdtest022.rpt
字号:
- 8 - C 17 OR2 s 0 4 0 1 ~904~2
- 3 - C 17 OR2 0 4 0 3 :904
- 1 - C 17 AND2 s 0 2 0 4 ~929~1
- 4 - C 17 OR2 s 0 4 0 1 ~929~2
- 4 - C 22 AND2 s ! 0 3 0 1 ~954~1
- 1 - C 15 AND2 s ! 0 2 0 1 ~954~2
- 2 - C 15 OR2 0 4 0 5 :954
- 3 - C 22 OR2 s ! 0 2 0 1 ~979~1
- 7 - C 22 OR2 s ! 0 4 0 1 ~979~2
- 6 - C 22 OR2 ! 0 4 0 4 :979
- 5 - C 17 AND2 s 0 2 0 5 ~1004~1
- 7 - C 14 OR2 s 0 4 0 1 ~1004~2
- 1 - C 13 OR2 0 3 0 5 :1026
- 6 - C 16 OR2 s ! 0 4 0 3 ~1029~1
- 6 - C 17 AND2 s 0 3 0 1 ~1054~1
- 3 - C 14 AND2 s 0 3 0 1 ~1054~2
- 4 - C 14 OR2 0 4 0 2 :1054
- 5 - C 22 OR2 ! 0 3 0 4 :1076
- 2 - C 20 OR2 0 3 0 4 :1079
- 1 - C 24 AND2 s 0 2 0 1 ~1080~1
- 4 - C 16 OR2 s 0 4 0 1 ~1080~2
- 4 - C 24 OR2 0 4 0 2 :1080
- 7 - C 16 AND2 ! 0 3 0 11 :1102
- 3 - C 24 OR2 s 0 3 0 2 ~1193~1
- 2 - C 18 OR2 s 0 2 0 4 ~1193~2
- 8 - C 22 OR2 s ! 0 4 0 2 ~1193~3
- 8 - C 14 OR2 s 0 4 0 1 ~1193~4
- 2 - C 14 OR2 s 0 4 0 1 ~1193~5
- 5 - C 23 OR2 0 4 0 2 :1193
- 3 - C 18 OR2 s 0 3 0 1 ~1194~1
- 5 - C 24 OR2 s 0 4 0 2 ~1194~2
- 6 - C 14 OR2 s ! 0 3 0 4 ~1195~1
- 5 - C 07 OR2 0 4 0 2 :1195
- 1 - C 18 AND2 s ! 0 3 0 3 ~1196~1
- 4 - C 18 OR2 s 0 3 0 1 ~1197~1
- 5 - C 18 OR2 0 3 0 2 :1197
- 5 - C 14 AND2 s ! 0 3 0 1 ~1198~1
- 1 - C 14 OR2 s 0 4 0 2 ~1198~2
- 5 - C 02 OR2 s 0 4 0 2 ~1198~3
- 1 - C 16 OR2 s 0 4 0 3 ~1198~4
- 2 - C 16 OR2 s ! 0 4 0 3 ~1199~1
- 4 - C 23 OR2 s 0 2 0 1 ~1199~2
- 5 - C 09 DFFE + 0 1 0 1 secondo7 (:1200)
- 6 - C 23 DFFE + 0 1 0 1 secondo6 (:1201)
- 6 - C 24 DFFE + 0 2 0 1 secondo5 (:1202)
- 6 - C 07 DFFE + 0 1 0 1 secondo4 (:1203)
- 3 - C 03 DFFE + 0 2 0 1 secondo3 (:1204)
- 7 - C 18 DFFE + 0 1 0 1 secondo2 (:1205)
- 6 - C 02 DFFE + 0 3 0 1 secondo1 (:1206)
- 6 - C 04 DFFE + 0 2 0 1 secondo0 (:1207)
- 7 - C 24 OR2 0 4 0 1 :1226
- 7 - C 03 OR2 0 4 0 1 :1228
- 7 - C 02 OR2 0 4 0 1 :1230
- 7 - C 04 OR2 0 4 0 1 :1231
- 7 - C 06 OR2 ! 0 3 0 9 :1240
- 8 - C 10 OR2 0 4 0 3 :1254
- 6 - C 10 OR2 s ! 0 4 0 1 ~1275~1
- 7 - C 10 AND2 s ! 0 2 0 1 ~1275~2
- 1 - C 10 OR2 0 4 0 4 :1275
- 6 - C 12 OR2 s ! 0 4 0 2 ~1296~1
- 2 - C 12 OR2 s 0 4 0 1 ~1296~2
- 1 - C 01 OR2 ! 0 2 0 4 :1296
- 6 - C 01 AND2 0 3 0 3 :1317
- 4 - C 12 OR2 s ! 0 3 0 1 ~1338~1
- 5 - C 12 OR2 0 4 0 5 :1338
- 5 - C 10 OR2 0 3 0 3 :1359
- 8 - C 12 OR2 ! 0 4 0 5 :1379
- 3 - C 10 OR2 ! 0 3 0 4 :1380
- 2 - C 09 AND2 ! 0 3 0 6 :1400
- 3 - C 09 AND2 0 4 0 2 :1458
- 7 - C 05 OR2 s 0 3 0 2 ~1467~1
- 5 - C 08 OR2 s 0 4 0 1 ~1467~2
- 6 - C 08 OR2 s 0 3 0 1 ~1467~3
- 2 - C 08 OR2 0 3 0 2 :1467
- 3 - C 05 OR2 0 4 0 2 :1468
- 2 - C 01 OR2 s 0 3 0 1 ~1469~1
- 3 - C 01 OR2 s 0 4 0 1 ~1469~2
- 7 - C 01 OR2 0 4 0 2 :1469
- 1 - C 05 AND2 s ! 0 3 0 4 ~1470~1
- 1 - C 03 OR2 0 3 0 2 :1470
- 2 - C 05 OR2 s 0 3 0 1 ~1471~1
- 6 - C 05 OR2 0 4 0 2 :1471
- 3 - C 08 OR2 s 0 2 0 1 ~1472~1
- 8 - C 08 OR2 0 4 0 2 :1472
- 8 - C 01 OR2 s 0 4 0 3 ~1473~1
- 2 - C 04 OR2 0 3 0 2 :1473
- 4 - C 09 DFFE + 0 1 0 1 minuteho7 (:1474)
- 7 - C 08 DFFE + 0 1 0 1 minuteho6 (:1475)
- 5 - C 05 DFFE + 0 1 0 1 minuteho5 (:1476)
- 4 - C 01 DFFE + 0 1 0 1 minuteho4 (:1477)
- 2 - C 03 DFFE + 0 1 0 1 minuteho3 (:1478)
- 4 - C 05 DFFE + 0 1 0 1 minuteho2 (:1479)
- 4 - C 08 DFFE + 0 1 0 1 minuteho1 (:1480)
- 3 - C 04 DFFE + 0 1 0 1 minuteho0 (:1481)
- 8 - C 06 AND2 ! 0 3 0 8 :1912
- 7 - C 09 OR2 s 0 4 0 1 ~1922~1
- 8 - C 09 OR2 s 0 4 0 1 ~1922~2
- 8 - C 23 OR2 s 0 4 0 1 ~1923~1
- 8 - C 24 OR2 s 0 4 0 1 ~1924~1
- 8 - C 07 OR2 s 0 4 0 1 ~1925~1
- 8 - C 03 OR2 s 0 4 0 1 ~1926~1
- 8 - C 18 OR2 s 0 4 0 1 ~1927~1
- 8 - C 02 OR2 s 0 4 0 1 ~1928~1
- 8 - C 04 OR2 s 0 4 0 1 ~1929~1
- 1 - C 09 DFFE + 0 4 1 1 :1930
- 2 - C 23 DFFE + 0 4 1 1 :1931
- 2 - C 24 DFFE + 0 4 1 1 :1932
- 4 - C 07 DFFE + 0 4 1 1 :1933
- 5 - C 03 DFFE + 0 4 1 1 :1934
- 6 - C 18 DFFE + 0 4 1 1 :1935
- 1 - C 02 DFFE + 0 4 1 1 :1936
- 1 - C 04 DFFE + 0 4 1 1 :1937
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\jtdtest022.rpt
jtdtest022
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 9/ 96( 9%) 24/ 48( 50%) 10/ 48( 20%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 39/ 96( 40%) 33/ 48( 68%) 30/ 48( 62%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\jtdtest022.rpt
jtdtest022
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 65 clk
Device-Specific Information: d:\dragon\jtdtest022.rpt
jtdtest022
** EQUATIONS **
clk : INPUT;
-- Node name is 'i0'
-- Equation name is 'i0', type is output
i0 = _LC4_A8;
-- Node name is 'i1'
-- Equation name is 'i1', type is output
i1 = _LC2_C6;
-- Node name is 'i2'
-- Equation name is 'i2', type is output
i2 = _LC3_C6;
-- Node name is ':146' = 'k0'
-- Equation name is 'k0', location is LC4_A16, type is buried.
k0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !k0 & !_LC4_A13;
-- Node name is ':145' = 'k1'
-- Equation name is 'k1', location is LC3_A16, type is buried.
k1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = k0 & !k1 & !_LC4_A13
# !k0 & k1 & !_LC4_A13;
-- Node name is ':144' = 'k2'
-- Equation name is 'k2', location is LC5_A16, type is buried.
k2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = k2 & !_LC2_A16 & !_LC4_A13
# !k2 & _LC2_A16 & !_LC4_A13;
-- Node name is ':143' = 'k3'
-- Equation name is 'k3', location is LC6_A16, type is buried.
k3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !k2 & k3 & !_LC4_A13
# k3 & !_LC2_A16 & !_LC4_A13
# k2 & !k3 & _LC2_A16 & !_LC4_A13;
-- Node name is ':142' = 'k4'
-- Equation name is 'k4', location is LC1_A20, type is buried.
k4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = k4 & !_LC1_A16 & !_LC4_A13
# !k4 & _LC1_A16 & !_LC4_A13;
-- Node name is ':141' = 'k5'
-- Equation name is 'k5', location is LC3_A20, type is buried.
k5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !k4 & k5 & !_LC4_A13
# k5 & !_LC1_A16 & !_LC4_A13
# k4 & !k5 & _LC1_A16 & !_LC4_A13;
-- Node name is ':140' = 'k6'
-- Equation name is 'k6', location is LC8_A13, type is buried.
k6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = k6 & !_LC2_A20 & !_LC4_A13
# !k6 & _LC2_A20 & !_LC4_A13;
-- Node name is ':139' = 'k7'
-- Equation name is 'k7', location is LC7_A13, type is buried.
k7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !k6 & k7 & !_LC4_A13
# k7 & !_LC2_A20 & !_LC4_A13
# k6 & !k7 & _LC2_A20 & !_LC4_A13;
-- Node name is ':138' = 'k8'
-- Equation name is 'k8', location is LC5_A13, type is buried.
k8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = k8 & !_LC3_A13 & !_LC4_A13
# !k8 & _LC3_A13 & !_LC4_A13;
-- Node name is ':137' = 'k9'
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