📄 jtdtest021.rpt
字号:
- 6 - C 01 OR2 s 0 4 0 1 ~821~1
- 4 - C 01 OR2 0 3 0 2 :821
- 1 - C 01 OR2 s 0 4 0 1 ~822~1
- 2 - C 01 OR2 s 0 4 0 1 ~822~2
- 8 - C 01 OR2 0 4 0 2 :822
- 4 - C 03 OR2 s 0 4 0 2 ~823~1
- 7 - C 11 OR2 s 0 4 0 1 ~823~2
- 6 - C 03 OR2 0 3 0 2 :823
- 4 - C 19 DFFE + 0 1 0 1 secondo7 (:824)
- 3 - C 04 DFFE + 0 1 0 1 secondo6 (:825)
- 1 - C 10 DFFE + 0 2 0 1 secondo5 (:826)
- 8 - C 11 DFFE + 0 1 0 1 secondo4 (:827)
- 1 - C 09 DFFE + 0 1 0 1 secondo3 (:828)
- 7 - C 01 DFFE + 0 1 0 1 secondo2 (:829)
- 5 - C 01 DFFE + 0 1 0 1 secondo1 (:830)
- 7 - C 03 DFFE + 0 1 0 1 secondo0 (:831)
- 5 - C 10 OR2 0 4 0 1 :850
- 3 - C 14 AND2 0 3 0 11 :859
- 7 - A 16 OR2 0 3 0 1 :893
- 8 - A 16 OR2 0 4 0 4 :902
- 6 - A 16 OR2 0 3 0 4 :903
- 4 - A 16 OR2 0 4 0 4 :904
- 3 - A 10 DFFE + 0 2 0 13 secondstr2 (:906)
- 1 - A 23 DFFE + 0 2 0 8 secondstr1 (:907)
- 1 - A 04 DFFE + 0 2 0 12 secondstr0 (:908)
- 3 - A 16 OR2 ! 0 3 0 4 :920
- 5 - A 16 OR2 ! 0 3 0 3 :921
- 1 - A 16 AND2 0 3 0 3 :925
- 1 - A 18 OR2 ! 0 2 0 3 :941
- 7 - A 02 OR2 ! 0 3 0 1 :952
- 3 - A 18 OR2 0 4 0 1 :988
- 4 - A 18 OR2 s 0 3 0 1 ~992~1
- 7 - A 18 OR2 0 4 0 1 :1009
- 2 - A 18 OR2 0 3 0 1 :1022
- 8 - A 18 OR2 s 0 4 0 1 ~1023~1
- 6 - A 18 OR2 0 3 0 2 :1023
- 1 - A 13 AND2 s 0 2 0 1 ~1024~1
- 5 - A 13 AND2 s 0 1 0 1 ~1024~2
- 7 - A 13 OR2 0 4 0 3 :1024
- 2 - A 13 DFFE + 0 4 0 12 secondh3 (:1028)
- 6 - A 13 DFFE + 0 4 0 11 secondh2 (:1029)
- 4 - A 13 DFFE + 0 3 0 11 secondh1 (:1030)
- 3 - A 13 DFFE + 0 1 0 13 secondh0 (:1031)
- 2 - A 20 OR2 0 3 0 2 :1054
- 3 - A 20 OR2 ! 0 4 0 3 :1055
- 6 - A 20 DFFE + 0 3 0 9 minuteh2 (:1075)
- 1 - A 20 DFFE + 0 3 0 10 minuteh1 (:1076)
- 4 - A 20 DFFE + 0 3 0 10 minuteh0 (:1077)
- 2 - C 21 AND2 0 3 0 10 :1081
- 1 - C 21 OR2 ! 0 4 0 8 :1173
- 6 - C 17 OR2 0 4 0 2 :1240
- 6 - C 21 OR2 s 0 4 0 4 ~1241~1
- 1 - C 17 OR2 0 4 0 2 :1242
- 3 - C 21 OR2 s 0 3 0 5 ~1243~1
- 5 - C 21 OR2 s 0 4 0 2 ~1244~1
- 4 - C 21 OR2 0 4 0 2 :1245
- 3 - C 19 DFFE + 0 1 0 1 minuteho7 (:1247)
- 3 - C 17 DFFE + 0 1 0 1 minuteho6 (:1248)
- 3 - C 10 DFFE + 0 2 0 1 minuteho5 (:1249)
- 2 - C 17 DFFE + 0 1 0 1 minuteho4 (:1250)
- 1 - C 23 DFFE + 0 2 0 1 minuteho3 (:1251)
- 8 - C 21 DFFE + 0 2 0 1 minuteho2 (:1252)
- 7 - C 21 DFFE + 0 1 0 1 minuteho1 (:1253)
- 1 - C 20 DFFE + 0 2 0 1 minuteho0 (:1254)
- 6 - C 10 OR2 0 4 0 1 :1273
- 4 - C 23 OR2 0 4 0 1 :1275
- 8 - C 20 OR2 0 4 0 1 :1278
- 1 - C 24 OR2 ! 0 4 0 10 :1287
- 5 - C 24 OR2 ! 0 4 0 3 :1313
- 2 - C 15 OR2 s 0 4 0 1 ~1427~1
- 1 - C 15 AND2 ! 0 2 0 14 :1427
- 3 - C 24 OR2 s 0 4 0 2 ~1518~1
- 6 - C 24 OR2 s 0 4 0 2 ~1519~1
- 2 - C 24 OR2 s ! 0 4 0 1 ~1520~1
- 2 - C 20 OR2 s 0 3 0 2 ~1520~2
- 4 - C 24 OR2 s 0 4 0 2 ~1521~1
- 8 - C 24 OR2 s 0 4 0 2 ~1522~1
- 7 - C 24 OR2 s 0 4 0 2 ~1523~1
- 3 - C 15 OR2 s 0 4 0 3 ~1524~1
- 2 - C 22 DFFE + 0 1 0 1 secondho7 (:1525)
- 4 - C 04 DFFE + 0 2 0 1 secondho6 (:1526)
- 4 - C 10 DFFE + 0 2 0 1 secondho5 (:1527)
- 3 - C 20 DFFE + 0 2 0 1 secondho4 (:1528)
- 3 - C 23 DFFE + 0 2 0 1 secondho3 (:1529)
- 2 - C 08 DFFE + 0 2 0 1 secondho2 (:1530)
- 4 - C 02 DFFE + 0 2 0 1 secondho1 (:1531)
- 4 - C 15 DFFE + 0 2 0 1 secondho0 (:1532)
- 7 - C 04 OR2 0 4 0 1 :1550
- 8 - C 10 OR2 0 4 0 1 :1551
- 7 - C 20 OR2 0 4 0 1 :1552
- 8 - C 23 OR2 0 4 0 1 :1553
- 8 - C 08 OR2 0 4 0 1 :1554
- 7 - C 02 OR2 0 4 0 1 :1555
- 8 - C 15 OR2 0 4 0 1 :1556
- 5 - C 19 OR2 s 0 4 0 1 ~1569~1
- 6 - C 19 OR2 s 0 4 0 1 ~1569~2
- 8 - C 19 OR2 s 0 4 0 1 ~1569~3
- 5 - C 04 OR2 s 0 4 0 1 ~1570~1
- 6 - C 04 OR2 s 0 3 0 1 ~1570~2
- 7 - C 10 OR2 s 0 4 0 1 ~1571~1
- 5 - C 20 OR2 s 0 4 0 1 ~1572~1
- 6 - C 20 OR2 s 0 3 0 1 ~1572~2
- 7 - C 23 OR2 s 0 4 0 1 ~1573~1
- 4 - C 08 OR2 s 0 4 0 1 ~1574~1
- 5 - C 08 OR2 s 0 4 0 1 ~1574~2
- 5 - C 02 OR2 s 0 4 0 1 ~1575~1
- 6 - C 02 OR2 s 0 3 0 1 ~1575~2
- 8 - C 03 OR2 s 0 4 0 1 ~1576~1
- 1 - C 22 DFFE + 0 4 1 1 :1577
- 2 - C 04 DFFE + 0 4 1 1 :1578
- 2 - C 10 DFFE + 0 4 1 1 :1579
- 4 - C 20 DFFE + 0 4 1 1 :1580
- 5 - C 23 DFFE + 0 4 1 1 :1581
- 6 - C 08 DFFE + 0 4 1 1 :1582
- 1 - C 02 DFFE + 0 4 1 1 :1583
- 5 - C 03 DFFE + 0 4 1 1 :1584
- 1 - C 08 AND2 ! 0 4 0 10 :1595
- 2 - C 05 DFFE + 0 3 1 0 :1601
- 3 - C 08 DFFE + 0 3 1 0 :1602
- 4 - B 05 OR2 s 0 3 0 1 ~1613~1
- 8 - B 04 OR2 s 0 4 0 1 ~1626~1
- 1 - B 04 OR2 ! 0 4 0 1 :1626
- 7 - B 05 OR2 ! 0 4 0 6 :1630
- 4 - B 04 AND2 s 0 2 0 1 ~1647~1
- 5 - B 04 OR2 s 0 4 0 1 ~1647~2
- 2 - B 04 OR2 0 4 0 6 :1647
- 7 - B 04 OR2 ! 0 3 0 1 :1666
- 7 - B 09 AND2 s ! 0 2 0 3 ~1667~1
- 8 - B 05 OR2 s 0 4 0 1 ~1667~2
- 6 - B 05 OR2 ! 0 4 0 6 :1667
- 4 - B 01 DFFE + 0 3 1 0 :1713
- 2 - B 05 DFFE + 0 3 1 0 :1714
- 1 - B 05 DFFE + 0 3 1 0 :1715
- 3 - B 04 DFFE + 0 3 1 0 :1716
- 6 - B 04 DFFE + 0 3 1 0 :1717
- 3 - B 05 DFFE + 0 3 1 0 :1718
- 8 - A 02 OR2 ! 0 4 0 1 :1729
- 1 - A 10 OR2 s 0 3 0 1 ~1742~1
- 2 - A 02 OR2 ! 0 4 0 6 :1746
- 5 - A 02 OR2 ! 0 3 0 2 :1760
- 8 - A 10 OR2 s 0 2 0 2 ~1762~1
- 6 - A 02 OR2 s 0 2 0 1 ~1762~2
- 1 - A 02 OR2 ! 0 4 0 6 :1762
- 6 - A 04 OR2 ! 0 3 0 1 :1781
- 5 - A 18 OR2 s ! 0 2 0 3 ~1782~1
- 7 - A 04 OR2 s 0 4 0 1 ~1782~2
- 8 - A 04 OR2 0 4 0 6 :1782
- 2 - A 04 DFFE + 0 3 1 0 :1829
- 5 - A 04 DFFE + 0 3 1 0 :1830
- 4 - A 04 DFFE + 0 3 1 0 :1831
- 3 - A 02 DFFE + 0 3 1 0 :1832
- 4 - A 02 DFFE + 0 3 1 0 :1833
- 3 - A 04 DFFE + 0 3 1 0 :1834
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\jtdtest021.rpt
jtdtest021
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 11/ 48( 22%) 10/ 48( 20%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 2/ 96( 2%) 20/ 48( 41%) 6/ 48( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 28/ 96( 29%) 21/ 48( 43%) 13/ 48( 27%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\jtdtest021.rpt
jtdtest021
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 87 clk
Device-Specific Information: d:\dragon\jtdtest021.rpt
jtdtest021
** EQUATIONS **
clk : INPUT;
-- Node name is ':46' = 'i0'
-- Equation name is 'i0', location is LC5_C14, type is buried.
i0 = DFFE(!i0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':45' = 'i1'
-- Equation name is 'i1', location is LC7_C14, type is buried.
i1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !i0 & i1 & !_LC4_C14
# i0 & !i1 & !_LC4_C14;
-- Node name is ':44' = 'i2'
-- Equation name is 'i2', location is LC6_C14, type is buried.
i2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !i1 & i2 & !_LC4_C14
# !i0 & i2 & !_LC4_C14
# i0 & i1 & !i2 & !_LC4_C14;
-- Node name is 'jtdm0'
-- Equation name is 'jtdm0', type is output
jtdm0 = _LC3_B5;
-- Node name is 'jtdm1'
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