📄 jtdtest01.rpt
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# !i10 & i11 & !i12 & !i13
# i10 & i12 & !i13
# !i11 & i12 & !i13;
-- Node name is ':324'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ021);
_EQ021 = i186 & !_LC7_C6
# _LC7_C9
# _LC2_C9;
-- Node name is '~325~1'
-- Equation name is '~325~1', location is LC5_C9, type is buried.
-- synthesized logic cell
_LC5_C9 = LCELL( _EQ022);
_EQ022 = i10 & i12 & !i13
# i10 & i11 & !i13
# i10 & i11 & i12
# !i11 & i12 & !i13;
-- Node name is ':325'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ023);
_EQ023 = _LC6_C11
# i185 & !_LC7_C6
# _LC5_C9;
-- Node name is '~326~1'
-- Equation name is '~326~1', location is LC1_C11, type is buried.
-- synthesized logic cell
_LC1_C11 = LCELL( _EQ024);
_EQ024 = i10 & i12 & !i13
# i10 & i11 & i12;
-- Node name is ':326'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = LCELL( _EQ025);
_EQ025 = i184 & !_LC7_C6
# _LC1_C11
# _LC7_C11;
-- Node name is '~327~1'
-- Equation name is '~327~1', location is LC1_C6, type is buried.
-- synthesized logic cell
!_LC1_C6 = _LC1_C6~NOT;
_LC1_C6~NOT = LCELL( _EQ026);
_EQ026 = !i10 & !i11 & !i12 & !i13
# i11 & !i12 & i13
# !i10 & i11 & i13
# i10 & !i12 & i13
# i10 & !i11 & i13
# i10 & i11 & !i12
# !i10 & i11 & i12
# !i10 & i12 & i13
# !i11 & i12 & i13;
-- Node name is ':327'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ027);
_EQ027 = i183 & !_LC7_C6
# _LC1_C6;
-- Node name is '~328~1'
-- Equation name is '~328~1', location is LC6_C2, type is buried.
-- synthesized logic cell
_LC6_C2 = LCELL( _EQ028);
_EQ028 = _LC1_C2
# _LC2_C6
# i182 & !_LC7_C11;
-- Node name is '~329~1'
-- Equation name is '~329~1', location is LC2_C6, type is buried.
-- synthesized logic cell
_LC2_C6 = LCELL( _EQ029);
_EQ029 = _LC5_C6
# _LC6_C6;
-- Node name is '~329~2'
-- Equation name is '~329~2', location is LC2_C2, type is buried.
-- synthesized logic cell
_LC2_C2 = LCELL( _EQ030);
_EQ030 = _LC1_C2
# _LC7_C11
# _LC2_C6
# _LC6_C9;
-- Node name is '~329~3'
-- Equation name is '~329~3', location is LC3_C2, type is buried.
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ031);
_EQ031 = i181 & !_LC7_C6
# _LC2_C2;
-- Node name is ':330'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = LCELL( _EQ032);
_EQ032 = _LC1_C6
# _LC5_C6
# i180 & !_LC7_C6;
-- Node name is ':447'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ033);
_EQ033 = !i20 & !i21 & i22;
-- Node name is ':491'
-- Equation name is '_LC4_C3', type is buried
!_LC4_C3 = _LC4_C3~NOT;
_LC4_C3~NOT = LCELL( _EQ034);
_EQ034 = i21 & !_LC2_C3
# i20 & i22 & !_LC2_C3
# !i20 & !i22 & !_LC2_C3;
-- Node name is '~558~1'
-- Equation name is '~558~1', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ035);
_EQ035 = !i20 & i21 & i22
# i20 & !i21 & i22
# i21 & i22 & i286;
-- Node name is '~558~2'
-- Equation name is '~558~2', location is LC7_C8, type is buried.
-- synthesized logic cell
_LC7_C8 = LCELL( _EQ036);
_EQ036 = i21 & !i22
# !i20 & !i21 & i22;
-- Node name is ':559'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ037);
_EQ037 = _LC1_C5
# _LC3_C5
# i285 & !_LC4_C3;
-- Node name is ':560'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = LCELL( _EQ038);
_EQ038 = !i20 & i21
# !i20 & !i22
# i21 & i22 & i284;
-- Node name is '~561~1'
-- Equation name is '~561~1', location is LC2_C3, type is buried.
-- synthesized logic cell
_LC2_C3 = LCELL( _EQ039);
_EQ039 = i21 & !i22
# i20 & !i21 & i22
# !i20 & i21
# !i20 & !i22;
-- Node name is ':561'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = LCELL( _EQ040);
_EQ040 = i283 & !_LC4_C3
# _LC2_C3;
-- Node name is '~562~1'
-- Equation name is '~562~1', location is LC5_C5, type is buried.
-- synthesized logic cell
_LC5_C5 = LCELL( _EQ041);
_EQ041 = i20 & !i22
# i22 & i282
# i20 & i282
# !i21 & i282;
-- Node name is ':562'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ042);
_EQ042 = _LC1_C5
# _LC3_C5
# _LC5_C5;
-- Node name is ':563'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ043);
_EQ043 = !i20 & !i21
# !i22
# i20 & i21 & i281;
-- Node name is '~564~1'
-- Equation name is '~564~1', location is LC1_C5, type is buried.
-- synthesized logic cell
_LC1_C5 = LCELL( _EQ044);
_EQ044 = i20 & !i21 & i22
# !i20 & i21 & i22
# !i20 & !i21 & !i22;
-- Node name is ':564'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ045);
_EQ045 = i280 & !_LC4_C3
# _LC2_C3;
-- Node name is ':615'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( _EQ046, GLOBAL( clk), VCC, VCC, VCC);
_EQ046 = _LC5_C7 & _LC6_C7
# i287 & !_LC4_C3 & !_LC6_C7;
-- Node name is ':616'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = DFFE( _EQ047, GLOBAL( clk), VCC, VCC, VCC);
_EQ047 = _LC2_C8 & _LC6_C7
# !_LC6_C7 & _LC7_C8
# _LC4_C8 & !_LC6_C7;
-- Node name is ':617'
-- Equation name is '_LC3_C7', type is buried
_LC3_C7 = DFFE( _EQ048, GLOBAL( clk), VCC, VCC, VCC);
_EQ048 = _LC2_C7 & _LC6_C7
# _LC2_C5 & !_LC6_C7;
-- Node name is ':618'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = DFFE( _EQ049, GLOBAL( clk), VCC, VCC, VCC);
_EQ049 = _LC2_C11 & _LC6_C7
# _LC5_C11 & !_LC6_C7;
-- Node name is ':619'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( _EQ050, GLOBAL( clk), VCC, VCC, VCC);
_EQ050 = _LC4_C6 & _LC6_C7
# !_LC6_C7 & _LC7_C3;
-- Node name is ':620'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = DFFE( _EQ051, GLOBAL( clk), VCC, VCC, VCC);
_EQ051 = _LC5_C9 & _LC6_C7
# _LC6_C2 & _LC6_C7
# _LC4_C5 & !_LC6_C7;
-- Node name is ':621'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _EQ052, GLOBAL( clk), VCC, VCC, VCC);
_EQ052 = _LC3_C2 & _LC6_C7
# _LC2_C9 & _LC6_C7
# _LC5_C12 & !_LC6_C7;
-- Node name is ':622'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( _EQ053, GLOBAL( clk), VCC, VCC, VCC);
_EQ053 = _LC3_C6 & _LC6_C7
# _LC3_C3 & !_LC6_C7;
Project Information d:\dragon\jtdtest01.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,057K
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