📄 jtdtest.rpt
字号:
- 2 - A 04 AND2 ! 0 3 0 5 :459
- 3 - A 01 OR2 s 0 3 0 1 ~526~1
- 7 - A 01 OR2 0 3 0 2 :526
- 4 - A 05 OR2 0 4 0 2 :527
- 2 - A 05 OR2 0 4 0 2 :528
- 5 - A 05 OR2 0 4 0 2 :529
- 1 - A 01 OR2 0 4 0 2 :530
- 4 - A 04 OR2 s 0 3 0 1 ~531~1
- 5 - A 04 OR2 0 4 0 2 :531
- 7 - A 11 OR2 0 4 0 2 :532
- 8 - A 04 DFFE + 0 1 0 1 i287 (:533)
- 8 - A 01 DFFE + 0 1 0 1 i286 (:534)
- 7 - A 05 DFFE + 0 1 0 1 i285 (:535)
- 3 - A 05 DFFE + 0 1 0 1 i284 (:536)
- 1 - A 05 DFFE + 0 1 0 1 i283 (:537)
- 2 - A 01 DFFE + 0 1 0 1 i282 (:538)
- 6 - A 04 DFFE + 0 1 0 1 i281 (:539)
- 8 - A 11 DFFE + 0 1 0 1 i280 (:540)
- 7 - A 04 DFFE + 0 3 1 0 :582
- 5 - A 01 DFFE + 0 2 1 0 :583
- 6 - A 05 DFFE + 0 2 1 0 :584
- 8 - A 05 DFFE + 0 2 1 0 :585
- 1 - A 11 DFFE + 0 2 1 0 :586
- 4 - A 01 DFFE + 0 2 1 0 :587
- 1 - A 04 DFFE + 0 2 1 0 :588
- 3 - A 11 DFFE + 0 2 1 0 :589
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\jtdtest.rpt
jtdtest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 15/ 48( 31%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 5/ 96( 5%) 18/ 48( 37%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\jtdtest.rpt
jtdtest
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 40 clk
Device-Specific Information: d:\dragon\jtdtest.rpt
jtdtest
** EQUATIONS **
clk : INPUT;
-- Node name is ':60' = 'i10'
-- Equation name is 'i10', location is LC2_C12, type is buried.
i10 = DFFE(!i10, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':59' = 'i11'
-- Equation name is 'i11', location is LC1_C10, type is buried.
i11 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !i10 & i11
# i10 & !i11 & !_LC1_C12
# i10 & !i11 & !i13;
-- Node name is ':58' = 'i12'
-- Equation name is 'i12', location is LC3_C10, type is buried.
i12 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !i11 & i12 & !_LC2_A11
# !i10 & i12 & !_LC2_A11
# i10 & i11 & !i12 & !_LC2_A11;
-- Node name is ':57' = 'i13'
-- Equation name is 'i13', location is LC6_C9, type is buried.
i13 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !i13 & _LC1_C9
# !i10 & i13 & !_LC1_C9
# i13 & !_LC1_C9 & !_LC1_C12;
-- Node name is ':363' = 'i20'
-- Equation name is 'i20', location is LC4_A11, type is buried.
i20 = DFFE(!i20, GLOBAL( clk), VCC, VCC, _LC2_A11);
-- Node name is ':362' = 'i21'
-- Equation name is 'i21', location is LC6_A11, type is buried.
i21 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, _LC2_A11);
_EQ004 = i20 & !i21
# !i20 & i21;
-- Node name is ':361' = 'i22'
-- Equation name is 'i22', location is LC5_A11, type is buried.
i22 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, _LC2_A11);
_EQ005 = !i20 & i22
# !i21 & i22
# i20 & i21 & !i22;
-- Node name is ':306' = 'i180'
-- Equation name is 'i180', location is LC8_C9, type is buried.
i180 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC7_C9
# _LC5_C10;
-- Node name is ':305' = 'i181'
-- Equation name is 'i181', location is LC3_C1, type is buried.
i181 = DFFE( _LC8_C1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':304' = 'i182'
-- Equation name is 'i182', location is LC6_C1, type is buried.
i182 = DFFE( _LC5_C1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':303' = 'i183'
-- Equation name is 'i183', location is LC5_C8, type is buried.
i183 = DFFE( _LC3_C8, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':302' = 'i184'
-- Equation name is 'i184', location is LC7_C8, type is buried.
i184 = DFFE( _LC6_C8, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':301' = 'i185'
-- Equation name is 'i185', location is LC7_C12, type is buried.
i185 = DFFE( _LC6_C12, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':300' = 'i186'
-- Equation name is 'i186', location is LC8_C10, type is buried.
i186 = DFFE( _LC2_C10, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':299' = 'i187'
-- Equation name is 'i187', location is LC8_C8, type is buried.
i187 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = i187 & !_LC4_C9;
-- Node name is ':540' = 'i280'
-- Equation name is 'i280', location is LC8_A11, type is buried.
i280 = DFFE( _LC7_A11, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':539' = 'i281'
-- Equation name is 'i281', location is LC6_A4, type is buried.
i281 = DFFE( _LC5_A4, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':538' = 'i282'
-- Equation name is 'i282', location is LC2_A1, type is buried.
i282 = DFFE( _LC1_A1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':537' = 'i283'
-- Equation name is 'i283', location is LC1_A5, type is buried.
i283 = DFFE( _LC5_A5, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':536' = 'i284'
-- Equation name is 'i284', location is LC3_A5, type is buried.
i284 = DFFE( _LC2_A5, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':535' = 'i285'
-- Equation name is 'i285', location is LC7_A5, type is buried.
i285 = DFFE( _LC4_A5, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':534' = 'i286'
-- Equation name is 'i286', location is LC8_A1, type is buried.
i286 = DFFE( _LC7_A1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':533' = 'i287'
-- Equation name is 'i287', location is LC8_A4, type is buried.
i287 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = i287 & !_LC2_A4;
-- Node name is 'k'
-- Equation name is 'k', type is output
k = _LC6_A1;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC3_C9;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC2_C11;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC7_C1;
-- Node name is 'out13'
-- Equation name is 'out13', type is output
out13 = _LC4_C8;
-- Node name is 'out14'
-- Equation name is 'out14', type is output
out14 = _LC1_C8;
-- Node name is 'out15'
-- Equation name is 'out15', type is output
out15 = _LC8_C12;
-- Node name is 'out16'
-- Equation name is 'out16', type is output
out16 = _LC4_C10;
-- Node name is 'out17'
-- Equation name is 'out17', type is output
out17 = _LC2_C8;
-- Node name is 'out20'
-- Equation name is 'out20', type is output
out20 = _LC3_A11;
-- Node name is 'out21'
-- Equation name is 'out21', type is output
out21 = _LC1_A4;
-- Node name is 'out22'
-- Equation name is 'out22', type is output
out22 = _LC4_A1;
-- Node name is 'out23'
-- Equation name is 'out23', type is output
out23 = _LC1_A11;
-- Node name is 'out24'
-- Equation name is 'out24', type is output
out24 = _LC8_A5;
-- Node name is 'out25'
-- Equation name is 'out25', type is output
out25 = _LC6_A5;
-- Node name is 'out26'
-- Equation name is 'out26', type is output
out26 = _LC5_A1;
-- Node name is 'out27'
-- Equation name is 'out27', type is output
out27 = _LC7_A4;
-- Node name is '|lpm_add_sub:591|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C9', type is buried
!_LC1_C9 = _LC1_C9~NOT;
_LC1_C9~NOT = LCELL( _EQ009);
_EQ009 = !i11
# !i10
# !i12;
-- Node name is ':20'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = DFFE(!_LC6_A1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':113'
-- Equation name is '_LC7_C10', type is buried
!_LC7_C10 = _LC7_C10~NOT;
_LC7_C10~NOT = LCELL( _EQ010);
_EQ010 = i11
# i13
# !i12
# i10;
-- Node name is '~165~1'
-- Equation name is '~165~1', location is LC1_C12, type is buried.
-- synthesized logic cell
_LC1_C12 = LCELL( _EQ011);
_EQ011 = !i11 & !i12;
-- Node name is ':179'
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = LCELL( _EQ012);
_EQ012 = i10 & i13 & _LC1_C12;
-- Node name is '~201~1'
-- Equation name is '~201~1', location is LC2_C9, type is buried.
-- synthesized logic cell
_LC2_C9 = LCELL( _EQ013);
_EQ013 = i13
# i12
# i11
# i10;
-- Node name is ':201'
-- Equation name is '_LC4_C9', type is buried
!_LC4_C9 = _LC4_C9~NOT;
_LC4_C9~NOT = LCELL( _EQ014);
_EQ014 = _LC2_C9 & !_LC5_C9 & !_LC5_C10 & !_LC7_C10;
-- Node name is '~292~1'
-- Equation name is '~292~1', location is LC5_C10, type is buried.
-- synthesized logic cell
_LC5_C10 = LCELL( _EQ015);
_EQ015 = !i11 & !i12 & i13
# !i10 & i11 & !i13
# i10 & !i11 & i12 & !i13
# i11 & !i12 & !i13;
-- Node name is ':292'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = LCELL( _EQ016);
_EQ016 = _LC7_C10
# _LC5_C10
# i186 & !_LC4_C9;
-- Node name is '~293~1'
-- Equation name is '~293~1', location is LC5_C12, type is buried.
-- synthesized logic cell
_LC5_C12 = LCELL( _EQ017);
_EQ017 = _LC4_C12
# _LC7_C10;
-- Node name is ':293'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = LCELL( _EQ018);
_EQ018 = i185 & !_LC4_C9
# _LC3_C12
# _LC5_C12;
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