📄 jtdtest02.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\dragon\jtdtest02.rpt
jtdtest02
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
31 - - C -- OUTPUT 0 1 0 0 i0
27 - - C -- OUTPUT 0 1 0 0 i1
32 - - C -- OUTPUT 0 1 0 0 i2
26 - - C -- OUTPUT 0 1 0 0 i3
30 - - C -- OUTPUT 0 1 0 0 out10
78 - - C -- OUTPUT 0 1 0 0 out11
79 - - C -- OUTPUT 0 1 0 0 out12
28 - - C -- OUTPUT 0 1 0 0 out13
83 - - C -- OUTPUT 0 1 0 0 out14
80 - - C -- OUTPUT 0 1 0 0 out15
82 - - C -- OUTPUT 0 1 0 0 out16
81 - - C -- OUTPUT 0 1 0 0 out17
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\dragon\jtdtest02.rpt
jtdtest02
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 13 AND2 0 0 1 5 |lpm_add_sub:2575|addcore:adder|:66
- 2 - C 13 OR2 0 1 1 3 |lpm_add_sub:2575|addcore:adder|:70
- 7 - C 13 OR2 0 2 1 3 |lpm_add_sub:2575|addcore:adder|:71
- 1 - C 13 OR2 0 3 1 2 |lpm_add_sub:2575|addcore:adder|:72
- 5 - C 07 DFFE + 0 3 0 11 second3 (:31)
- 3 - C 02 AND2 s 0 4 0 1 second2~1 (~32~1)
- 2 - C 07 DFFE + 0 2 0 12 second2 (:32)
- 2 - C 09 DFFE + 0 1 0 13 second1 (:33)
- 6 - C 09 DFFE + 0 0 0 13 second0 (:34)
- 6 - C 07 AND2 0 4 0 5 :48
- 7 - C 04 OR2 ! 0 4 0 2 :62
- 8 - C 07 AND2 0 4 0 3 :128
- 6 - C 02 OR2 ! 0 3 0 9 :175
- 2 - C 12 AND2 0 2 0 1 :262
- 1 - C 07 OR2 s 0 4 0 1 ~266~1
- 4 - C 03 OR2 s 0 4 0 1 ~266~2
- 6 - C 03 OR2 0 4 0 2 :266
- 3 - C 07 OR2 s 0 4 0 2 ~267~1
- 5 - C 02 OR2 0 4 0 2 :267
- 5 - C 04 OR2 s 0 4 0 3 ~268~1
- 4 - C 04 OR2 0 4 0 2 :268
- 2 - C 04 OR2 0 4 0 2 :269
- 3 - C 12 OR2 0 4 0 2 :270
- 1 - C 12 OR2 s 0 2 0 1 ~271~1
- 1 - C 09 OR2 s 0 4 0 2 ~271~2
- 7 - C 07 OR2 s 0 4 0 2 ~271~3
- 4 - C 07 OR2 s 0 4 0 3 ~272~1
- 1 - C 03 OR2 s 0 3 0 2 ~272~2
- 6 - C 11 DFFE + 0 1 0 1 secondo7 (:273)
- 7 - C 03 DFFE + 0 1 0 1 secondo6 (:274)
- 7 - C 02 DFFE + 0 1 0 1 secondo5 (:275)
- 6 - C 04 DFFE + 0 1 0 1 secondo4 (:276)
- 3 - C 04 DFFE + 0 1 0 1 secondo3 (:277)
- 4 - C 12 DFFE + 0 1 0 1 secondo2 (:278)
- 3 - C 09 DFFE + 0 2 0 1 secondo1 (:279)
- 3 - C 03 DFFE + 0 2 0 1 secondo0 (:280)
- 2 - C 06 DFFE + 0 3 0 8 minute2 (:351)
- 7 - C 06 DFFE + 0 3 0 7 minute1 (:352)
- 5 - C 06 DFFE + 0 1 0 8 minute0 (:353)
- 7 - C 11 OR2 ! 0 4 0 5 :449
- 2 - C 11 AND2 0 2 0 2 :507
- 1 - C 06 OR2 0 4 0 2 :516
- 4 - C 11 AND2 s 0 1 0 3 ~517~1
- 1 - C 02 OR2 0 3 0 2 :517
- 6 - C 06 OR2 0 4 0 2 :518
- 1 - C 11 OR2 s 0 3 0 4 ~519~1
- 1 - C 10 OR2 0 3 0 2 :519
- 5 - C 12 OR2 s 0 4 0 2 ~520~1
- 3 - C 06 OR2 0 4 0 2 :521
- 5 - C 11 DFFE + 0 1 0 1 minuteo7 (:523)
- 8 - C 06 DFFE + 0 1 0 1 minuteo6 (:524)
- 2 - C 02 DFFE + 0 1 0 1 minuteo5 (:525)
- 7 - C 01 DFFE + 0 1 0 1 minuteo4 (:526)
- 2 - C 10 DFFE + 0 1 0 1 minuteo3 (:527)
- 6 - C 12 DFFE + 0 2 0 1 minuteo2 (:528)
- 4 - C 06 DFFE + 0 1 0 1 minuteo1 (:529)
- 4 - C 10 DFFE + 0 2 0 1 minuteo0 (:530)
- 7 - C 10 AND2 ! 0 2 0 1 :2391
- 4 - C 13 OR2 s ! 0 4 0 10 ~2401~1
- 3 - C 13 AND2 s 0 3 0 15 ~2401~2
- 8 - C 11 OR2 s 0 4 0 1 ~2465~1
- 8 - C 03 OR2 s 0 4 0 1 ~2466~1
- 8 - C 02 OR2 s 0 4 0 1 ~2467~1
- 8 - C 04 OR2 s 0 4 0 1 ~2468~1
- 8 - C 10 OR2 s 0 4 0 1 ~2469~1
- 7 - C 12 OR2 s 0 4 0 1 ~2470~1
- 4 - C 09 OR2 s 0 4 0 1 ~2471~1
- 6 - C 10 OR2 s 0 4 0 1 ~2472~1
- 5 - C 03 OR2 s 0 4 0 1 ~2472~2
- 3 - C 11 DFFE + 0 4 1 1 :2559
- 2 - C 03 DFFE + 0 3 1 1 :2560
- 4 - C 02 DFFE + 0 3 1 1 :2561
- 1 - C 04 DFFE + 0 3 1 1 :2562
- 3 - C 10 DFFE + 0 3 1 1 :2563
- 8 - C 12 DFFE + 0 4 1 1 :2564
- 7 - C 09 DFFE + 0 4 1 1 :2565
- 5 - C 10 DFFE + 0 3 1 0 :2566
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\dragon\jtdtest02.rpt
jtdtest02
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 10/ 96( 10%) 30/ 48( 62%) 4/ 48( 8%) 0/16( 0%) 12/16( 75%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\dragon\jtdtest02.rpt
jtdtest02
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 clk
Device-Specific Information: d:\dragon\jtdtest02.rpt
jtdtest02
** EQUATIONS **
clk : INPUT;
-- Node name is 'i0'
-- Equation name is 'i0', type is output
i0 = _LC6_C13;
-- Node name is 'i1'
-- Equation name is 'i1', type is output
i1 = _LC2_C13;
-- Node name is 'i2'
-- Equation name is 'i2', type is output
i2 = _LC7_C13;
-- Node name is 'i3'
-- Equation name is 'i3', type is output
i3 = _LC1_C13;
-- Node name is ':530' = 'minuteo0'
-- Equation name is 'minuteo0', location is LC4_C10, type is buried.
minuteo0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC7_C11 & minuteo0
# _LC1_C11;
-- Node name is ':529' = 'minuteo1'
-- Equation name is 'minuteo1', location is LC4_C6, type is buried.
minuteo1 = DFFE( _LC3_C6, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':528' = 'minuteo2'
-- Equation name is 'minuteo2', location is LC6_C12, type is buried.
minuteo2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_C11
# _LC5_C12;
-- Node name is ':527' = 'minuteo3'
-- Equation name is 'minuteo3', location is LC2_C10, type is buried.
minuteo3 = DFFE( _LC1_C10, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':526' = 'minuteo4'
-- Equation name is 'minuteo4', location is LC7_C1, type is buried.
minuteo4 = DFFE( _LC6_C6, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':525' = 'minuteo5'
-- Equation name is 'minuteo5', location is LC2_C2, type is buried.
minuteo5 = DFFE( _LC1_C2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':524' = 'minuteo6'
-- Equation name is 'minuteo6', location is LC8_C6, type is buried.
minuteo6 = DFFE( _LC1_C6, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':523' = 'minuteo7'
-- Equation name is 'minuteo7', location is LC5_C11, type is buried.
minuteo7 = DFFE( _LC2_C11, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':353' = 'minute0'
-- Equation name is 'minute0', location is LC5_C6, type is buried.
minute0 = DFFE(!minute0, GLOBAL( clk), VCC, VCC, _LC6_C7);
-- Node name is ':352' = 'minute1'
-- Equation name is 'minute1', location is LC7_C6, type is buried.
minute1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, _LC6_C7);
_EQ003 = minute0 & minute2
# minute0 & minute1
# !minute0 & !minute1;
-- Node name is ':351' = 'minute2'
-- Equation name is 'minute2', location is LC2_C6, type is buried.
minute2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, _LC6_C7);
_EQ004 = minute0 & minute2
# minute1 & minute2
# !minute0 & !minute1 & !minute2;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC5_C10;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
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