verilog uartrx.txt

verilogHDL编写的串口检测程序

module uartrx(clkfenpin,rst,dain,led); //串口接收
input  clkfenpin,rst,dain;
output[3:0] led;

reg[7:0] receiveddata;
reg flush,flag,over;
reg[5:0] cbit,rbit;

initial begin
receiveddata=0;flush=0;flag=0;over=0;cbit=0;rbit=0;
end
always @(posedge clkfenpin or negedge rst) //
begin
if(!rst)
  begin
  flush<=0;
receiveddata<=0;
  end
else
	begin
	//flush=1;
	 if (over==1)
		begin
		 
		if (cbit==7)
			begin
			  cbit=0;
			  over=0;
			end
			else
			begin
			 cbit=cbit+1;
			end
		end
	  else
		  begin
		
				if (flag==0)
					begin
					 if (cbit==7)     //detect start bit
							begin
							cbit=0;
							flag=1;
							end
					   if (dain==0)          //start bit ?
							 begin
							 cbit=cbit+1;
							 end
						else 
							begin
							cbit=0;
							end
						
					end
				else
					begin
					
						
					if (cbit==15)
						begin 
						 cbit=0;
						 if (rbit==8)   //if end of receive
							  begin
							rbit=0;
							//flush=!flush;
							flag=0;
							over=1;
							  end
						 else
						begin
						  receiveddata[rbit]=dain;
							rbit=rbit+1;
						   
									 if (receiveddata==49)
										begin
										 flush=!flush;
										end
							end
							 
							  end
		
						
					else
						 begin
					         cbit=cbit+1;
					      end	
					end
					
		  end
		
	end

end


assign led[0] = receiveddata[4];
assign led[1] = receiveddata[5];
assign led[2] = receiveddata[6];
assign led[3] = receiveddata[7];
endmodule


module jishuqi(clk,sr_out);  //检测时钟程序
	input clk;
	output sr_out;

	// Declare the shift register
	reg [15:0] sr;
    reg clk0;
	// Shift everything over, load the incoming bit
	always @ (posedge clk)
	begin			
		if (sr>=162) 
			begin
				sr= 0;
				clk0=!clk0;
			  end
			else
			begin
				sr= sr+1;
        	  end

	end
assign sr_out=clk0;	
endmodule