📄 hardware.lst
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// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
00000210 .IRAM
.PUBLIC R_InterruptStatus
00000210 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.DEFINE C_RampDelayTime 32
.DEFINE C_QueueSize 144
00000211 00 00 .VAR R_Queue
00000212 00 00 00 00 .DW C_QueueSize-1 DUP(0)
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00 00
000002A1 00 00 .VAR R_ReadIndex
000002A2 00 00 .VAR R_WriteIndex
0000B2AA .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,r2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
0000B2AA 09 93 11 02 r1 = R_Queue
0000B2AC 40 94 r2 = 0
L_ClearQueueLoop?:
0000B2AD D1 D4 [r1++] = r2
0000B2AE 09 43 A1 02 cmp r1, R_Queue+C_QueueSize
0000B2B0 44 4E jne L_ClearQueueLoop?
0000B2B1 40 92 r1 = 0
0000B2B2 19 D3 A1 02 [R_ReadIndex] = r1
0000B2B4 19 D3 A2 02 [R_WriteIndex] = r1
0000B2B6 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
0000B2B7 12 95 A1 02 r2 = [R_ReadIndex]
0000B2B9 12 45 A2 02 cmp r2,[R_WriteIndex]
0000B2BB 0D 5E je L_RQ_QueueEmpty
0000B2BC 0A 05 11 02 r2 += R_Queue // get queue data address
0000B2BE C2 92 r1 = [r2]
0000B2BF 12 95 A1 02 r2 = [R_ReadIndex]
0000B2C1 41 04 r2 += 1
0000B2C2 0A 45 90 00 cmp r2, C_QueueSize
0000B2C4 01 4E jne L_RQ_NotQueueBottom
0000B2C5 40 94 r2 = 0
L_RQ_NotQueueBottom:
0000B2C6 1A D5 A1 02 [R_ReadIndex] = r2
//r2 = 0x0000 // get queue data
0000B2C8 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
0000B2C9 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
0000B2CA 12 95 A1 02 r2 = [R_ReadIndex]
0000B2CC 12 45 A2 02 cmp r2,[R_WriteIndex]
0000B2CE 03 5E je L_RQ_QueueEmpty?
0000B2CF 0A 05 11 02 r2 += R_Queue // get queue data index
0000B2D1 C2 92 r1 = [r2]
L_RQ_QueueEmpty?:
0000B2D2 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
0000B2D3 12 95 A2 02 r2 = [R_WriteIndex] // put data to queue
0000B2D5 0A 05 11 02 r2 += R_Queue
0000B2D7 C2 D2 [r2] = r1
0000B2D8 12 95 A2 02 r2 = [R_WriteIndex]
0000B2DA 41 04 r2 += 1
0000B2DB 0A 45 90 00 cmp r2, C_QueueSize
0000B2DD 01 4E jne L_WQ_NotQueueBottom
0000B2DE 40 94 r2 = 0
L_WQ_NotQueueBottom:
0000B2DF 1A D5 A2 02 [R_WriteIndex] = r2
0000B2E1 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
0000B2E2 11 93 A1 02 r1 = [R_ReadIndex]
0000B2E4 11 43 A2 02 cmp r1,[R_WriteIndex]
0000B2E6 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
0000B2E7 11 93 A1 02 r1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
0000B2E9 05 4E jnz L_TQ_JudgeCond2
0000B2EA 11 93 A2 02 r1 = [R_WriteIndex]
0000B2EC 09 43 8F 00 cmp r1, C_QueueSize-1 // Cond1
0000B2EE 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
0000B2EF 11 93 A1 02 r1 = [R_ReadIndex]
0000B2F1 41 22 r1 -=1
0000B2F2 11 43 A2 02 cmp r1,[R_WriteIndex]
0000B2F4 02 5E je L_TQ_QueueFull
0000B2F5 40 92 r1 = 0 // not Full, not empty
0000B2F6 90 9A retf
L_TQ_QueueFull:
0000B2F7 41 92 r1 = 1 // full
0000B2F8 90 9A retf
L_TQ_QueueEmpty:
0000B2F9 42 92 r1 = 2 // empty
0000B2FA 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
// or F_SACM_A2000_Initial:
// Note: The following functions are the partial code of original
// initial subroutine. (H/W setting part)
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