orm2.vhd

本程序用VHDL语言实现二输入或门的逻辑功能

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ORM2 IS
  PORT(A,B:IN STD_LOGIC;C:OUT STD_LOGIC);
END ENTITY ORM2;
ARCHITECTURE ART1 OF ORM2 IS
  BEGIN
  
  C<=A OR B;
END ARCHITECTURE ART1;