gal_300f.vhq

一个组合逻辑实例,完成地址选择,读写信号产生等时序

-- Jed2svhdl, ispLEVER version 5.01 
-- Header :
--    File Name :
--       gal_300f 
--    Circuit Name :
--       gal_300f 
--    Last Update :
--       Sun Dec 03 17:52:05 2006
--    Device Information :
--       PLD Type P16V8AS
--    Manufacturer and Part Information :
--       LAT GAL16V8Z-15QS GAL
--    Delay Model Selected :MAX
--    Jedec Information :
--	ispLEVER 5.1.02.70.06.06.SP2006.02 Lattice Semiconductor Corp.
--	JEDEC file for: P16V8AS V9.0
--	Created on: Sun Dec 03 17:51:58 2006
--	
--	gal_300f.bls 
--	
-- endHeader

LIBRARY j2svlib;
USE j2svlib.j2svlib.all;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE std.textio.all;
--------------------------------------------------------------------------
--                                                                      --
--              MAIN PLD NETLIST MODULE                                 --
--                                                                      --
--------------------------------------------------------------------------

ENTITY gal_300f IS
   GENERIC (
-- Delay Parameters:
--   MAX delay used
       tpLH06 : time := 0 ns;
       tpHL06 : time := 0 ns;
       tpLH09 : time := 0 ns;
       tpHL09 : time := 0 ns;
       tpLH_iob : time := 0 ns;
       tpHL_iob : time := 0 ns;
       tpLH03 : time := 0 ns;
       tpHL03 : time := 0 ns;
       tpLH05 : time := 0 ns;
       tpHL05 : time := 0 ns;
       tpLH_inco_lump : time := 15 ns;
       tpHL_inco_lump : time := 15 ns;
       tpLH_oe : time := 15 ns;
       tpHL_oe : time := 15 ns;
       tpLH_oe_pterm : time := 15 ns;
       tpHL_oe_pterm : time := 15 ns);
   PORT (
	POW1: IN STD_LOGIC := '0';
	POW0: IN STD_LOGIC := '0';
	RD: IN STD_LOGIC := '0';
	WR: IN STD_LOGIC := '0';
	A0: IN STD_LOGIC := '0';
	A1: IN STD_LOGIC := '0';
	A2: IN STD_LOGIC := '0';
	PIN08: IN STD_LOGIC := '0';
	PIN09: IN STD_LOGIC := '0';
	PIN11: IN STD_LOGIC := '0';
	PIN12: INOUT STD_LOGIC;
	PIN13: INOUT STD_LOGIC;
	PIN14: INOUT STD_LOGIC;
	CS0: OUT STD_LOGIC;
	CS2: OUT STD_LOGIC;
	PIN17: INOUT STD_LOGIC;
	POW_EN: OUT STD_LOGIC;
	CS1: OUT STD_LOGIC);

--Pin Assignments:
    -- alias PIN01 is: STD_LOGIC POW1;
    -- alias PIN02 is: STD_LOGIC POW0;
    -- alias PIN03 is: STD_LOGIC RD;
    -- alias PIN04 is: STD_LOGIC WR;
    -- alias PIN05 is: STD_LOGIC A0;
    -- alias PIN06 is: STD_LOGIC A1;
    -- alias PIN07 is: STD_LOGIC A2;
    -- alias PIN15 is: STD_LOGIC CS0;
    -- alias PIN16 is: STD_LOGIC CS2;
    -- alias PIN18 is: STD_LOGIC POW_EN;
    -- alias PIN19 is: STD_LOGIC CS1;

END gal_300f;

ARCHITECTURE structure OF gal_300f IS

-- Signal Declaration :
   SIGNAL  CS1_ODUMMY, POW_EN_ODUMMY, ST019_o, XOR018_o,
           ST018_o, ST016_o, ST015_o, PT032_1024_o, PT024_768_o,
           PT008_256_o, PT000_0_o, INBUF19_ob, INBUF19_o, INBUF18_ob,
           INBUF18_o, INBUF17_ob, INBUF17_o, INBUF14_ob, INBUF14_o,
           INBUF13_ob, INBUF13_o, INBUF12_ob, INBUF12_o, INBUF11_ob,
           INBUF11_o, INBUF09_ob, INBUF09_o, INBUF08_ob, INBUF08_o,
           INBUF07_ob, INBUF07_o, INBUF06_ob, INBUF06_o, INBUF05_ob,
           INBUF05_o, INBUF04_ob, INBUF04_o, INBUF03_ob, INBUF03_o,
           INBUF02_ob, INBUF02_o, INBUF01_ob, INBUF01_o
           : STD_LOGIC ;
   SIGNAL  PWR : STD_LOGIC := '1' ;
   SIGNAL  GND : STD_LOGIC := '0' ;
   SIGNAL  PWRUPSTATE : STD_LOGIC := '0' ;

--   PLD Netlist ---------
  BEGIN

--   Input Buffer:
      INBUF01_o <= POW1 after g_delay ( INBUF01_o,tpLH_iob,tpHL_iob);
      INBUF01_ob <=  not(POW1) after g_delay ( INBUF01_ob,tpLH_iob,tpHL_iob);
      INBUF02_o <= POW0 after g_delay ( INBUF02_o,tpLH_iob,tpHL_iob);
      INBUF02_ob <=  not(POW0) after g_delay ( INBUF02_ob,tpLH_iob,tpHL_iob);
      INBUF03_o <= RD after g_delay ( INBUF03_o,tpLH_iob,tpHL_iob);
      INBUF03_ob <=  not(RD) after g_delay ( INBUF03_ob,tpLH_iob,tpHL_iob);
      INBUF04_o <= WR after g_delay ( INBUF04_o,tpLH_iob,tpHL_iob);
      INBUF04_ob <=  not(WR) after g_delay ( INBUF04_ob,tpLH_iob,tpHL_iob);
      INBUF05_o <= A0 after g_delay ( INBUF05_o,tpLH_iob,tpHL_iob);
      INBUF05_ob <=  not(A0) after g_delay ( INBUF05_ob,tpLH_iob,tpHL_iob);
      INBUF06_o <= A1 after g_delay ( INBUF06_o,tpLH_iob,tpHL_iob);
      INBUF06_ob <=  not(A1) after g_delay ( INBUF06_ob,tpLH_iob,tpHL_iob);
      INBUF07_o <= A2 after g_delay ( INBUF07_o,tpLH_iob,tpHL_iob);
      INBUF07_ob <=  not(A2) after g_delay ( INBUF07_ob,tpLH_iob,tpHL_iob);
      INBUF08_o <= PIN08 after g_delay ( INBUF08_o,tpLH_iob,tpHL_iob);
      INBUF08_ob <=  not(PIN08) after g_delay ( INBUF08_ob,tpLH_iob,tpHL_iob);
      INBUF09_o <= PIN09 after g_delay ( INBUF09_o,tpLH_iob,tpHL_iob);
      INBUF09_ob <=  not(PIN09) after g_delay ( INBUF09_ob,tpLH_iob,tpHL_iob);
      INBUF11_o <= PIN11 after g_delay ( INBUF11_o,tpLH_iob,tpHL_iob);
      INBUF11_ob <=  not(PIN11) after g_delay ( INBUF11_ob,tpLH_iob,tpHL_iob);
      INBUF12_o <= PIN12 after g_delay ( INBUF12_o,tpLH_iob,tpHL_iob);
      INBUF12_ob <=  not(PIN12) after g_delay ( INBUF12_ob,tpLH_iob,tpHL_iob);
      INBUF13_o <= PIN13 after g_delay ( INBUF13_o,tpLH_iob,tpHL_iob);
      INBUF13_ob <=  not(PIN13) after g_delay ( INBUF13_ob,tpLH_iob,tpHL_iob);
      INBUF14_o <= PIN14 after g_delay ( INBUF14_o,tpLH_iob,tpHL_iob);
      INBUF14_ob <=  not(PIN14) after g_delay ( INBUF14_ob,tpLH_iob,tpHL_iob);
      INBUF17_o <= PIN17 after g_delay ( INBUF17_o,tpLH_iob,tpHL_iob);
      INBUF17_ob <=  not(PIN17) after g_delay ( INBUF17_ob,tpLH_iob,tpHL_iob);
      INBUF18_o <= POW_EN_ODUMMY after g_delay ( INBUF18_o,tpLH_iob,tpHL_iob);
      INBUF18_ob <=  not(POW_EN_ODUMMY) after g_delay ( INBUF18_ob,tpLH_iob,tpHL_iob);
      INBUF19_o <= CS1_ODUMMY after g_delay ( INBUF19_o,tpLH_iob,tpHL_iob);
      INBUF19_ob <=  not(CS1_ODUMMY) after g_delay ( INBUF19_ob,tpLH_iob,tpHL_iob);

--   Product Terms (AND array):
      PT000_0_o <= INBUF03_ob AND INBUF05_ob AND INBUF06_o AND INBUF07_ob after g_delay ( PT000_0_o,tpLH03,tpHL03);
      PT008_256_o <= INBUF02_ob AND INBUF01_ob after g_delay ( PT008_256_o,tpLH03,tpHL03);
      PT024_768_o <= INBUF05_ob AND INBUF06_ob AND INBUF07_o after g_delay ( PT024_768_o,tpLH03,tpHL03);
      PT032_1024_o <= INBUF04_ob AND INBUF05_o AND INBUF06_ob AND INBUF07_ob after g_delay ( PT032_1024_o,tpLH03,tpHL03);

--   Sum Terms (OR arrray):
      ST015_o <= PT032_1024_o after g_delay ( ST015_o,tpLH_inco_lump,tpHL_inco_lump);
      ST016_o <= PT024_768_o after g_delay ( ST016_o,tpLH_inco_lump,tpHL_inco_lump);
      ST018_o <= PT008_256_o after g_delay ( ST018_o,tpLH_inco_lump,tpHL_inco_lump);
      XOR018_o <= ST018_o XOR PWR after g_delay ( XOR018_o,tpLH06,tpHL06);
      ST019_o <= PT000_0_o after g_delay ( ST019_o,tpLH_inco_lump,tpHL_inco_lump);

--   Macro Cells:

--   Feedback Node:

--   Output Buffer:
      g_notif1( PIN12, GND, PWR, tpLH09,tpHL09);
      g_notif1( PIN13, GND, PWR, tpLH09,tpHL09);
      g_notif1( PIN14, GND, PWR, tpLH09,tpHL09);
      g_notif1( CS0, ST015_o, PWR, tpLH09,tpHL09);
      g_notif1( CS2, ST016_o, PWR, tpLH09,tpHL09);
      g_notif1( PIN17, GND, PWR, tpLH09,tpHL09);
      g_notif1( POW_EN_ODUMMY, XOR018_o, PWR, tpLH09,tpHL09);
      g_notif1( CS1_ODUMMY, ST019_o, PWR, tpLH09,tpHL09);
      POW_EN <= POW_EN_ODUMMY;
      CS1 <= CS1_ODUMMY;
END structure;