gal_300f.bl2

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#$ TOOL ispLEVER 5.1.02.70.06.06.SP2006.02
#$ DATE Sun Dec 03 17:53:46 2006
#$ TITLE gal_300f.bls 
#$ MODULE gal_300f
#$ PINS 11 POW_EN'o'  POW1 POW0 RD CS2'o'  CS1'o'  CS0'o'  A2 A1 A0 WR
#$ NODES 10 N_8'o'  N_6'o'  N_7'o'  N_2'o'  N_5'o'  I6>s_3_'o'  I6>s_4_'o'  I6>s_5_'o'  I6>s_6_'o'  I6>s_7_'o' 

.model gal_300f
.inputs POW1.BLIF POW0.BLIF RD.BLIF N_8.BLIF WR.BLIF N_2.BLIF N_5.BLIF N_7.BLIF \
N_6.BLIF A0.BLIF A1.BLIF A2.BLIF
.outputs POW_EN CS1 CS0 N_2 N_8 CS2 N_5 N_7 N_6 I6>s_3_ I6>s_4_ I6>s_5_ \
I6>s_6_ I6>s_7_
\

.subckt addr_select a_0_.BLIF=A0.BLIF a_1_.BLIF=A1.BLIF a_2_.BLIF=A2.BLIF s_0_=N_5 s_1_=N_7 s_2_=N_6 s_3_=I6>s_3_ s_4_=I6>s_4_ s_5_=I6>s_5_ s_6_=I6>s_6_ \
 s_7_=I6>s_7_
.names POW1.BLIF POW0.BLIF POW_EN
00 1
1- 0
-1 0
.names RD.BLIF N_8.BLIF CS1
1- 1
-1 1
00 0
.names WR.BLIF N_2.BLIF CS0
1- 1
-1 1
00 0
.names N_5.BLIF N_2
0 1
1 0
.names N_7.BLIF N_8
0 1
1 0
.names N_6.BLIF CS2
0 1
1 0
.end

.model addr_select
.inputs a_2_.BLIF a_1_.BLIF a_0_.BLIF
.outputs s_7_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_
.names s_7_
.names s_6_
.names s_5_
.names s_4_
.names s_3_
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_2_
100 1
-1- 0
0-- 0
--1 0
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_1_
010 1
-0- 0
1-- 0
--1 0
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_0_
001 1
-1- 0
1-- 0
--0 0
.end