addr_select.log

一个组合逻辑实例,完成地址选择,读写信号产生等时序

Starting EDIF2BLIF....
readEDIF ended normally.

Inspect circuit ADDR_SELECT
    Number of input ports   : 1
    Number of output ports  : 1
    Number of bidir ports   : 0
    Number of instances     : 23
    Number of nets          : 26

No design errors found in circuit ADDR_SELECT

WriteBLIF ended normally.