gal_300f.lci

一个组合逻辑实例,完成地址选择,读写信号产生等时序

[Device]
Family = plsiGal;
PartNumber = GAL16V8D-25QJ;
Package = 20PLCC;
PartType = GAL16V8D;
Speed = -25;
Operating_condition = COM;
Status = Production;

[Revision]
Parent = plsigal.lci;
DATE = 12/03/2006;
TIME = 17:53:25;
Source_Format = Schematic_VHDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]