addr_select.vm

一个组合逻辑实例,完成地址选择,读写信号产生等时序

//
// Written by Synplify
// Synplify 8.2.0, Build 035R.
// Sun Dec 03 17:53:40 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\isptools5_1\synpbase\lib\vhd\std.vhd "
// file 2 "\c:\gal_300f\addr_select.vhd "
// file 3 "\c:\isptools5_1\synpbase\lib\vhd\std1164.vhd "

`timescale 100 ps/100 ps
module IBUF (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* IBUF */

module OBUF (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* OBUF */

module AND2 (
  O,
  I0,
  I1
);
output O ;
input I0 ;
input I1 ;
wire O ;
wire I0 ;
wire I1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module INV (
  O,
  I0
);
output O ;
input I0 ;
wire O ;
wire I0 ;
wire VCC ;
wire GND ;
  assign #(1)  O = ~ I0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* INV */

module ADDR_SELECT (
  a,
  s
);
input [2:0] a ;
output [7:0] s ;
wire [2:0] a_i;
wire [2:0] a_c;
wire GND ;
wire s9 ;
wire s10 ;
wire s11 ;
wire s11_1 ;
wire s10_1 ;
wire s9_1 ;
wire VCC ;
//@1:1
  assign GND = 1'b0;
  IBUF \a_cZ[0]  (
	.O(a_c[0]),
	.I0(a[0])
);
  IBUF \a_cZ[1]  (
	.O(a_c[1]),
	.I0(a[1])
);
  IBUF \a_cZ[2]  (
	.O(a_c[2]),
	.I0(a[2])
);
  OBUF \s_cZ[0]  (
	.O(s[0]),
	.I0(s9)
);
  OBUF \s_cZ[1]  (
	.O(s[1]),
	.I0(s10)
);
  OBUF \s_cZ[2]  (
	.O(s[2]),
	.I0(s11)
);
  OBUF \s_cZ[3]  (
	.O(s[3]),
	.I0(GND)
);
  OBUF \s_cZ[4]  (
	.O(s[4]),
	.I0(GND)
);
  OBUF \s_cZ[5]  (
	.O(s[5]),
	.I0(GND)
);
  OBUF \s_cZ[6]  (
	.O(s[6]),
	.I0(GND)
);
  OBUF \s_cZ[7]  (
	.O(s[7]),
	.I0(GND)
);
  AND2 s11_0_a2_1 (
	.O(s11_1),
	.I0(a_i[1]),
	.I1(a_c[2])
);
  AND2 s11_0_a2 (
	.O(s11),
	.I0(s11_1),
	.I1(a_i[0])
);
  AND2 s10_0_a2_1 (
	.O(s10_1),
	.I0(a_i[2]),
	.I1(a_c[1])
);
  AND2 s10_0_a2 (
	.O(s10),
	.I0(s10_1),
	.I1(a_i[0])
);
  AND2 s9_0_a2_1 (
	.O(s9_1),
	.I0(a_i[2]),
	.I1(a_c[0])
);
  AND2 s9_0_a2 (
	.O(s9),
	.I0(s9_1),
	.I1(a_i[1])
);
  INV I_18 (
	.O(a_i[2]),
	.I0(a_c[2])
);
  INV I_16 (
	.O(a_i[0]),
	.I0(a_c[0])
);
  INV I_17 (
	.O(a_i[1]),
	.I0(a_c[1])
);
  assign VCC = 1'b1;
endmodule /* ADDR_SELECT */