gal_300f.vtl

一个组合逻辑实例,完成地址选择,读写信号产生等时序

-- NOTE: Do not edit this file.
-- Auto generated by Post-Route Verilog Simulation Models
--
vlog   -v C:/ispTOOLS5_1/ispcpld/pld/verilog/pldlib.v c:/gal_300f/gal_300f.vt
-- End