gal_300f.tfi

一个组合逻辑实例,完成地址选择,读写信号产生等时序

// TOOL:     sch2tf
// DATE:     2006-12-03 17:52:02 下午 
// TITLE:    
// MODULE:   gal_300f
// DESIGN:   gal_300f
// FILENAME: gal_300f.tfi
// PROJECT:  gal_300f
// VERSION:  1.3
// NOTE: DO NOT EDIT THIS FILE
//
// This file is generated by the Verilog Test Fixture Declarations process and 
// contains an I/O and instance declarations of the Verilog source file
// you selected from the Sources in Project list.
//
// This include file (.tfi) should be referenced by your text fixture using
// the `include compile directive using the syntax:  `include "<file_name>.tfi"
// If your design I/O changes, rerun the process to obtain new I/O and 
// instance declarations.


// Inputs
	reg A0;
	reg A1;
	reg A2;
	reg POW0;
	reg POW1;
	reg RD;
	reg WR;


// Outputs
	wire CS0;
	wire CS1;
	wire CS2;
	wire POW_EN;


// Bidirs


// Instantiate the UUT
	gal_300f UUT (
		.A0(A0), 
		.A1(A1), 
		.A2(A2), 
		.CS0(CS0), 
		.CS1(CS1), 
		.CS2(CS2), 
		.POW0(POW0), 
		.POW1(POW1), 
		.POW_EN(POW_EN), 
		.RD(RD), 
		.WR(WR)
	);


// Initialize Inputs
`ifdef auto_init

	initial begin
		A0 = 0;
		A1 = 0;
		A2 = 0;
		POW0 = 0;
		POW1 = 0;
		RD = 0;
		WR = 0;
	end

`endif