gal_300f.bl1

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#$ TOOL ispLEVER 5.1.02.70.06.06.SP2006.02
#$ DATE Sun Dec 03 17:53:46 2006
#$ TITLE gal_300f.bls 
#$ MODULE gal_300f
#$ PINS 11 POW_EN'o'  POW1 POW0 RD CS2'o'  CS1'o'  CS0'o'  A2 A1 A0 WR
#$ NODES 10 N_8'o'  N_6 N_7 N_2'o'  N_5 I6>s_3_ I6>s_4_ I6>s_5_ I6>s_6_ I6>s_7_
#$ INTERFACE addr_select  11 a_0_'i'  a_1_'i'  a_2_'i'  s_0_'o'  s_1_'o'  s_2_'o'  s_3_'o'  s_4_'o'  s_5_'o'  s_6_'o'  s_7_'o' 
#$ INSTANCE I6 addr_select 11 A0 A1 A2 N_5 N_7 N_6 I6>s_3_ I6>s_4_ I6>s_5_ I6>s_6_ I6>s_7_

.model gal_300f
.inputs POW1.BLIF POW0.BLIF RD.BLIF N_8.BLIF WR.BLIF N_2.BLIF N_5.BLIF N_7.BLIF \
N_6.BLIF
.outputs POW_EN CS1 CS0 N_2 N_8 CS2
.names POW1.BLIF POW0.BLIF POW_EN
00 1
1- 0
-1 0
.names RD.BLIF N_8.BLIF CS1
1- 1
-1 1
00 0
.names WR.BLIF N_2.BLIF CS0
1- 1
-1 1
00 0
.names N_5.BLIF N_2
0 1
1 0
.names N_7.BLIF N_8
0 1
1 0
.names N_6.BLIF CS2
0 1
1 0
.end