addr_select.vhd

一个组合逻辑实例,完成地址选择,读写信号产生等时序

library ieee;
use ieee.std_logic_1164.all;

entity ADDR_SELECT is
    port (a:in std_logic_vector(2 downto 0);
          s:out std_logic_vector(7 downto 0));
end;

architecture behavioral of ADDR_SELECT is
begin
process(a)
begin
  case a is
    when"001"=>s<="00000001";
    when"010"=>s<="00000010";
    when"100"=>s<="00000100";
    when others=>s<="00000000";
    end case;
end process;
end behavioral;