gal_300f.bls

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#$ TOOL SCH2BLF 5.1.51.05 
#$ TITLE gal_300f.bls 
#$ MODULE gal_300f 
#$ PINS 11  POW_EN POW1 POW0 RD CS2 CS1 CS0 A2 A1 A0 WR
#$ NODES 5 N_8 N_6 N_7 N_2 N_5 
#$ NODES 5 I6>s_3_ I6>s_4_ I6>s_5_ I6>s_6_ I6>s_7_
#$ INTERFACE addr_select 11 a_0_'i' a_1_'i' a_2_'i' s_0_'o' s_1_'o' \
#   s_2_'o' s_3_'o' s_4_'o' s_5_'o' s_6_'o' s_7_'o'
#$ INTERFACE g_2nor 3 A'i' B'i' YN'o'
#$ INTERFACE g_2or 3 A'i' B'i' Y'o'
#$ INTERFACE g_inv 2 A'i' YN'o'
#$ INSTANCE I6 addr_select 11 A0 A1 A2 N_5 N_7 N_6 I6>s_3_ I6>s_4_ \
#   I6>s_5_ I6>s_6_ I6>s_7_
#$ PRIMITIVE I7 g_2nor 3 POW1 POW0 POW_EN
#$ PRIMITIVE I4 g_2or 3 RD N_8 CS1
#$ PRIMITIVE I5 g_2or 3 WR N_2 CS0
#$ PRIMITIVE I1 g_inv 2 N_5 N_2
#$ PRIMITIVE I2 g_inv 2 N_7 N_8
#$ PRIMITIVE I3 g_inv 2 N_6 CS2
.model gal_300f

.end