addr_select.bl0

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#$ DATE Sun Dec 03 17:53:45 2006
#$ TOOL EDIF2BLIF version IspLever 1.0 
#$ MODULE addr_select
#$ PINS 11 a_2_ s_7_ a_1_ a_0_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_
#$ NODES 13 gnd_n_n s9 s10 s11 a_i_0__n a_i_1__n a_i_2__n a_c_0__n a_c_1__n a_c_2__n 
s11_1 s10_1 s9_1 
.model addr_select
.inputs a_2_.BLIF a_1_.BLIF a_0_.BLIF gnd_n_n.BLIF s9.BLIF s10.BLIF s11.BLIF a_i_0__n.BLIF a_i_1__n.BLIF \
  a_i_2__n.BLIF a_c_0__n.BLIF a_c_1__n.BLIF a_c_2__n.BLIF s11_1.BLIF s10_1.BLIF s9_1.BLIF  
.outputs s_7_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_ gnd_n_n s9 s10 \
  s11 a_i_0__n a_i_1__n a_i_2__n a_c_0__n a_c_1__n a_c_2__n s11_1 s10_1 s9_1
.names  a_0_.BLIF a_c_0__n
1 1
.names  a_1_.BLIF a_c_1__n
1 1
.names  a_2_.BLIF a_c_2__n
1 1
.names  s9.BLIF s_0_
1 1
.names  s10.BLIF s_1_
1 1
.names  s11.BLIF s_2_
1 1
.names  gnd_n_n.BLIF s_3_
1 1
.names  gnd_n_n.BLIF s_4_
1 1
.names  gnd_n_n.BLIF s_5_
1 1
.names  gnd_n_n.BLIF s_6_
1 1
.names  gnd_n_n.BLIF s_7_
1 1
.names  a_i_1__n.BLIF a_c_2__n.BLIF s11_1
11 1
.names  s11_1.BLIF a_i_0__n.BLIF s11
11 1
.names  a_i_2__n.BLIF a_c_1__n.BLIF s10_1
11 1
.names  s10_1.BLIF a_i_0__n.BLIF s10
11 1
.names  a_i_2__n.BLIF a_c_0__n.BLIF s9_1
11 1
.names  s9_1.BLIF a_i_1__n.BLIF s9
11 1
.names  a_c_2__n.BLIF a_i_2__n
0 1
.names  a_c_0__n.BLIF a_i_0__n
0 1
.names  a_c_1__n.BLIF a_i_1__n
0 1
.names  gnd_n_n
.end