addr_select.exf

一个组合逻辑实例,完成地址选择,读写信号产生等时序

Section Type   Array Num   Name                     Real Name          Base     Number     Increment
// -------------------------------------------------------------------------------------------------
      Port          1      a(2:0)                        a                  2          3            -1
      Port          2      s(7:0)                        s                  7          8            -1
End
Section Member   Rename                   Array-Notation          Array Number     Index
// -------------------------------------------------------------------------------------
        Port      a_2_                        a[2]                       1            0            
        Port      a_1_                        a[1]                       1            1            
        Port      a_0_                        a[0]                       1            2            
        Port      s_7_                        s[7]                       2            0            
        Port      s_6_                        s[6]                       2            1            
        Port      s_5_                        s[5]                       2            2            
        Port      s_4_                        s[4]                       2            3            
        Port      s_3_                        s[3]                       2            4            
        Port      s_2_                        s[2]                       2            5            
        Port      s_1_                        s[1]                       2            6            
        Port      s_0_                        s[0]                       2            7            
End
Section Cross Reference File
Design 'ADDR_SELECT' created Sun Dec 03 17:53:45 2006
   Type              New Name                               Original Name
// ----------------------------------------------------------------------
   Inst                   a_0_                                      a[0]
   Inst                   a_1_                                      a[1]
   Inst                   a_2_                                      a[2]
   Inst                   s_0_                                      s[0]
   Inst                   s_1_                                      s[1]
   Inst                   s_2_                                      s[2]
   Inst                   s_3_                                      s[3]
   Inst                   s_4_                                      s[4]
   Inst                   s_5_                                      s[5]
   Inst                   s_6_                                      s[6]
   Inst                   s_7_                                      s[7]
   Net                 gnd_n_n                                       GND
   Net                a_i_0__n                                    a_i[0]
   Net                a_i_1__n                                    a_i[1]
   Net                a_i_2__n                                    a_i[2]
   Net                a_c_0__n                                    a_c[0]
   Net                  a_0__n                                      a[0]
   Net                a_c_1__n                                    a_c[1]
   Net                  a_1__n                                      a[1]
   Net                a_c_2__n                                    a_c[2]
   Net                  s_0__n                                      s[0]
   Net                  s_1__n                                      s[1]
   Net                  s_2__n                                      s[2]
   Net                  s_3__n                                      s[3]
   Net                  s_4__n                                      s[4]
   Net                  s_5__n                                      s[5]
   Net                  s_6__n                                      s[6]
End
Section Type      Name
// ----------------------------------------------------------------------
        Input     a_2_
        Input     a_1_
        Input     a_0_
        Output     s_7_
        Output     s_6_
        Output     s_5_
        Output     s_4_
        Output     s_3_
        Output     s_2_
        Output     s_1_
        Output     s_0_
End