addr_select.vhm

一个组合逻辑实例,完成地址选择,读写信号产生等时序

--
-- Written by Synplicity
-- Sun Dec 03 17:53:40 2006
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= not I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity ADDR_SELECT is
port(
  a : in std_logic_vector (2 downto 0);
  s : out std_logic_vector (7 downto 0));
end ADDR_SELECT;

architecture beh of ADDR_SELECT is
  signal A_I : std_logic_vector (2 downto 0);
  signal A_C : std_logic_vector (2 downto 0);
  signal GND : std_logic ;
  signal S9 : std_logic ;
  signal S10 : std_logic ;
  signal S11 : std_logic ;
  signal S11_1 : std_logic ;
  signal S10_1 : std_logic ;
  signal S9_1 : std_logic ;
  signal VCC : std_logic ;
  component IBUF
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
  component OBUF
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
  component AND2
    port(
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic  );
  end component;
  component INV
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
begin
  GND <= '0';
  \II_a_cZ[0]\: IBUF port map (
      O => A_C(0),
      I0 => a(0));
  \II_a_cZ[1]\: IBUF port map (
      O => A_C(1),
      I0 => a(1));
  \II_a_cZ[2]\: IBUF port map (
      O => A_C(2),
      I0 => a(2));
  \II_s_cZ[0]\: OBUF port map (
      O => s(0),
      I0 => S9);
  \II_s_cZ[1]\: OBUF port map (
      O => s(1),
      I0 => S10);
  \II_s_cZ[2]\: OBUF port map (
      O => s(2),
      I0 => S11);
  \II_s_cZ[3]\: OBUF port map (
      O => s(3),
      I0 => GND);
  \II_s_cZ[4]\: OBUF port map (
      O => s(4),
      I0 => GND);
  \II_s_cZ[5]\: OBUF port map (
      O => s(5),
      I0 => GND);
  \II_s_cZ[6]\: OBUF port map (
      O => s(6),
      I0 => GND);
  \II_s_cZ[7]\: OBUF port map (
      O => s(7),
      I0 => GND);
  II_s11_0_a2_1: AND2 port map (
      O => S11_1,
      I0 => A_I(1),
      I1 => A_C(2));
  II_s11_0_a2: AND2 port map (
      O => S11,
      I0 => S11_1,
      I1 => A_I(0));
  II_s10_0_a2_1: AND2 port map (
      O => S10_1,
      I0 => A_I(2),
      I1 => A_C(1));
  II_s10_0_a2: AND2 port map (
      O => S10,
      I0 => S10_1,
      I1 => A_I(0));
  II_s9_0_a2_1: AND2 port map (
      O => S9_1,
      I0 => A_I(2),
      I1 => A_C(0));
  II_s9_0_a2: AND2 port map (
      O => S9,
      I0 => S9_1,
      I1 => A_I(1));
  II_I_18: INV port map (
      O => A_I(2),
      I0 => A_C(2));
  II_I_16: INV port map (
      O => A_I(0),
      I0 => A_C(0));
  II_I_17: INV port map (
      O => A_I(1),
      I0 => A_C(1));
  VCC <= '1';
end beh;