testfreq.tan.qmsg

利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 115 " "Warning: Circuit may not operate. Detected 115 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Dec_to_BCD:inst\|n4\[2\] LED:inst1\|dan\[4\] clk 2.271 ns " "Info: Found hold time violation between source  pin or register \"Dec_to_BCD:inst\|n4\[2\]\" and destination pin or register \"LED:inst1\|dan\[4\]\" for clock \"clk\" (Hold time is 2.271 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.741 ns + Largest " "Info: + Largest clock skew is 4.741 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.481 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 157; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns LED:inst1\|clk1 2 REG LC_X9_Y6_N2 17 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X9_Y6_N2; Fanout = 17; REG Node = 'LED:inst1\|clk1'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk LED:inst1|clk1 } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.806 ns) + CELL(0.711 ns) 7.481 ns LED:inst1\|dan\[4\] 3 REG LC_X10_Y7_N6 1 " "Info: 3: + IC(3.806 ns) + CELL(0.711 ns) = 7.481 ns; Loc. = LC_X10_Y7_N6; Fanout = 1; REG Node = 'LED:inst1\|dan\[4\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.517 ns" { LED:inst1|clk1 LED:inst1|dan[4] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.64 % ) " "Info: Total cell delay = 3.115 ns ( 41.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.366 ns ( 58.36 % ) " "Info: Total interconnect delay = 4.366 ns ( 58.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { clk LED:inst1|clk1 LED:inst1|dan[4] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|dan[4] } { 0.000ns 0.000ns 0.560ns 3.806ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 157; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns Dec_to_BCD:inst\|n4\[2\] 2 REG LC_X11_Y7_N7 7 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X11_Y7_N7; Fanout = 7; REG Node = 'Dec_to_BCD:inst\|n4\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk Dec_to_BCD:inst|n4[2] } "NODE_NAME" } } { "Dec_to_BCD.vhd" "" { Text "D:/Project/Quartus II/testfreq/Dec_to_BCD.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk Dec_to_BCD:inst|n4[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 Dec_to_BCD:inst|n4[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { clk LED:inst1|clk1 LED:inst1|dan[4] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|dan[4] } { 0.000ns 0.000ns 0.560ns 3.806ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk Dec_to_BCD:inst|n4[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 Dec_to_BCD:inst|n4[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "Dec_to_BCD.vhd" "" { Text "D:/Project/Quartus II/testfreq/Dec_to_BCD.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.261 ns - Shortest register register " "Info: - Shortest register to register delay is 2.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dec_to_BCD:inst\|n4\[2\] 1 REG LC_X11_Y7_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N7; Fanout = 7; REG Node = 'Dec_to_BCD:inst\|n4\[2\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Dec_to_BCD:inst|n4[2] } "NODE_NAME" } } { "Dec_to_BCD.vhd" "" { Text "D:/Project/Quartus II/testfreq/Dec_to_BCD.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 0.378 ns LED:inst1\|Mux23~23 2 COMB LC_X11_Y7_N7 1 " "Info: 2: + IC(0.000 ns) + CELL(0.378 ns) = 0.378 ns; Loc. = LC_X11_Y7_N7; Fanout = 1; COMB Node = 'LED:inst1\|Mux23~23'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.378 ns" { Dec_to_BCD:inst|n4[2] LED:inst1|Mux23~23 } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.590 ns) 1.690 ns LED:inst1\|Mux50~66 3 COMB LC_X10_Y7_N7 2 " "Info: 3: + IC(0.722 ns) + CELL(0.590 ns) = 1.690 ns; Loc. = LC_X10_Y7_N7; Fanout = 2; COMB Node = 'LED:inst1\|Mux50~66'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { LED:inst1|Mux23~23 LED:inst1|Mux50~66 } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.115 ns) 2.261 ns LED:inst1\|dan\[4\] 4 REG LC_X10_Y7_N6 1 " "Info: 4: + IC(0.456 ns) + CELL(0.115 ns) = 2.261 ns; Loc. = LC_X10_Y7_N6; Fanout = 1; REG Node = 'LED:inst1\|dan\[4\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { LED:inst1|Mux50~66 LED:inst1|dan[4] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.083 ns ( 47.90 % ) " "Info: Total cell delay = 1.083 ns ( 47.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.178 ns ( 52.10 % ) " "Info: Total interconnect delay = 1.178 ns ( 52.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.261 ns" { Dec_to_BCD:inst|n4[2] LED:inst1|Mux23~23 LED:inst1|Mux50~66 LED:inst1|dan[4] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.261 ns" { Dec_to_BCD:inst|n4[2] LED:inst1|Mux23~23 LED:inst1|Mux50~66 LED:inst1|dan[4] } { 0.000ns 0.000ns 0.722ns 0.456ns } { 0.000ns 0.378ns 0.590ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { clk LED:inst1|clk1 LED:inst1|dan[4] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|dan[4] } { 0.000ns 0.000ns 0.560ns 3.806ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk Dec_to_BCD:inst|n4[2] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 Dec_to_BCD:inst|n4[2] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.261 ns" { Dec_to_BCD:inst|n4[2] LED:inst1|Mux23~23 LED:inst1|Mux50~66 LED:inst1|dan[4] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.261 ns" { Dec_to_BCD:inst|n4[2] LED:inst1|Mux23~23 LED:inst1|Mux50~66 LED:inst1|dan[4] } { 0.000ns 0.000ns 0.722ns 0.456ns } { 0.000ns 0.378ns 0.590ns 0.115ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk wie\[1\] LED:inst1\|wei\[1\] 12.774 ns register " "Info: tco from clock \"clk\" to destination pin \"wie\[1\]\" through register \"LED:inst1\|wei\[1\]\" is 12.774 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.481 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 157; CLK Node = 'clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 160 -104 64 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns LED:inst1\|clk1 2 REG LC_X9_Y6_N2 17 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X9_Y6_N2; Fanout = 17; REG Node = 'LED:inst1\|clk1'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk LED:inst1|clk1 } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.806 ns) + CELL(0.711 ns) 7.481 ns LED:inst1\|wei\[1\] 3 REG LC_X10_Y8_N3 1 " "Info: 3: + IC(3.806 ns) + CELL(0.711 ns) = 7.481 ns; Loc. = LC_X10_Y8_N3; Fanout = 1; REG Node = 'LED:inst1\|wei\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.517 ns" { LED:inst1|clk1 LED:inst1|wei[1] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.64 % ) " "Info: Total cell delay = 3.115 ns ( 41.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.366 ns ( 58.36 % ) " "Info: Total interconnect delay = 4.366 ns ( 58.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { clk LED:inst1|clk1 LED:inst1|wei[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|wei[1] } { 0.000ns 0.000ns 0.560ns 3.806ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.069 ns + Longest register pin " "Info: + Longest register to pin delay is 5.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED:inst1\|wei\[1\] 1 REG LC_X10_Y8_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N3; Fanout = 1; REG Node = 'LED:inst1\|wei\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LED:inst1|wei[1] } "NODE_NAME" } } { "LED.vhd" "" { Text "D:/Project/Quartus II/testfreq/LED.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.945 ns) + CELL(2.124 ns) 5.069 ns wie\[1\] 2 PIN PIN_34 0 " "Info: 2: + IC(2.945 ns) + CELL(2.124 ns) = 5.069 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'wie\[1\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.069 ns" { LED:inst1|wei[1] wie[1] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/Project/Quartus II/testfreq/Block1.bdf" { { 216 640 816 232 "wie\[5..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 41.90 % ) " "Info: Total cell delay = 2.124 ns ( 41.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.945 ns ( 58.10 % ) " "Info: Total interconnect delay = 2.945 ns ( 58.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.069 ns" { LED:inst1|wei[1] wie[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.069 ns" { LED:inst1|wei[1] wie[1] } { 0.000ns 2.945ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { clk LED:inst1|clk1 LED:inst1|wei[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { clk clk~out0 LED:inst1|clk1 LED:inst1|wei[1] } { 0.000ns 0.000ns 0.560ns 3.806ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.069 ns" { LED:inst1|wei[1] wie[1] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.069 ns" { LED:inst1|wei[1] wie[1] } { 0.000ns 2.945ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 24 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 30 02:47:03 2007 " "Info: Processing ended: Thu Aug 30 02:47:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}